TI DS90UB903Q/DS90UB904Q：FPD-Link III串化解串器技术文档

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"TI-DS90UB904Q-Q1.pdf 是一款FPD-Link解串器，由德州仪器(TI)制造，适用于高速、高质量的视频数据传输。这款解串器与DS90UB903Q一起构成芯片组，提供10-43MHz的并行端口时钟支持，数据吞吐量范围为210Mbps到903Mbps。它可以在单个差分对上传输数据，并且包含了高速正向通道和双向控制通道，支持AC耦合的互联。" 文章详细介绍了DS90UB903Q/DS90UB904Q的主要特性： 1. **高速传输**：该设备支持10MHz至43MHz的输入并行端口时钟频率，最大数据传输速率可达903Mbps，确保了高速的数据传输性能。 2. **FPD-Link III接口**：芯片组采用FPD-Link III接口，能在单个差分对上同时处理高速正向数据和双向控制信号，提供高效的数据传输和控制。 3. **双向控制通道**：具备I2C支持的双向控制接口，允许设备接收和发送控制信息，提高系统的灵活性和交互性。 4. **长距离驱动**：可以驱动长达10米的屏蔽双绞线，适合远距离的视频信号传输。 5. **嵌入式时钟和DC平衡编码**：支持AC耦合连接，通过DC平衡编码提供稳定可靠的信号传输，确保视频质量。 6. **I2C兼容**：集成I2C兼容串行接口，便于与系统中的其他I2C设备通信，并且有一个硬件设备寻址引脚。 7. **多用途输入/输出**：提供多达4个通用输入/输出(GPI/GPO)，可以灵活配置用于各种控制功能。 8. **状态指示与诊断**：具有LOCK输出报告以指示连接状态，同时AT-SPEED BIST功能支持全速内置自检，增强系统诊断能力，保证了系统稳定运行。 TI-DS90UB904Q-Q1是一款高性能的FPD-Link解串器，特别适用于需要高速、长距离视频传输的图形主机控制器与显示模块之间的连接，其强大的双向控制和诊断功能使得在复杂系统设计中更具优势。

DS90UB903Q-Q1, DS90UB904Q-Q1

ZHCSB32E –JUNE 2010–REVISED APRIL 2013

www.ti.com.cn

Electrical Characteristics

(1)(2)(3)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)

High Level Input

= 3.0V to 3.6V 2.0 V

Voltage

Low Level Input

= 3.0V to 3.6V GND 0.8 V

Voltage

Input Current V

= 0V or 3.6V, V

= 3.0V to 3.6V -20 ±1 +20 µA

High Level Output

DDIO

= 3.0V to 3.6V, I

= −4 mA 2.4 V

DDIO

Voltage

Low Level Output

DDIO

= 3.0V to 3.6V, I

= +4 mA GND 0.4 V

Voltage

Serializer GPO

-24

Outputs

Output Short Circuit

OUT

= 0V mA

Current

Deserializer LVCMOS

-39

Outputs

TRI-STATE Output PDB = 0V,

LVCMOS Outputs -20 ±1 +20 µA

Current V

OUT

= 0V or V

LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)

High Level Input

= 1.71V to 1.89V 0.65 V

+0.3

Voltage

Low Level Input

= 1.71V to 1.89V GND 0.35 V

Voltage

Input Current V

= 0V or 1.89V, V

= 1.71V to 1.89V -20 ±1 +20 µA

High Level Output V

DDIO

= 1.71V to 1.89V, I

= −4 mA V

DDIO

Voltage 0.45

Low Level Output V

DDIO

= 1.71V to 1.89V Deserializer LVCMOS

GND 0.45 V

Voltage I

= +4 mA Outputs

Serializer GPO

-11

Outputs

Output Short Circuit

OUT

= 0V mA

Current

Deserializer LVCMOS

-20

Outputs

TRI-STATE Output PDB = 0V,

LVCMOS Outputs -20 ±1 +20 µA

Current V

OUT

= 0V or V

CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)

Output Differential

| R

= 100Ω (Figure 8) 268 340 412 mV

Voltage

Output Differential

ΔV

= 100Ω 1 50 mV

Voltage Unbalance

Output Differential V

DD (MIN)

- V

DD (MAX)

= 100Ω (Figure 8) V

- V

Offset Voltage V

OD (MAX)

OD (MIN)

ΔV

Offset Voltage

= 100Ω 1 50 mV

Unbalance

Output Short Circuit

DOUT+/- = 0V -27 mA

Current

Differential Internal

Termination Differential across DOUT+ and DOUT- 80 100 120 Ω

Resistance

CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except VOD, ΔVOD, VTH and VTL which are differential voltages.

(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T

= +25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not ensured.

DS90UB903Q-Q1, DS90UB904Q-Q1

www.ti.com.cn

ZHCSB32E –JUNE 2010–REVISED APRIL 2013

Electrical Characteristics

(1)(2)(3)

(continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

Differential Threshold

+90

High Voltage

(Figure 10) mV

Differential Threshold

-90

Low Voltage

Differential Input

RIN+ - RIN- 180 mV

Voltage Range

Input Current V

= V

or 0V, V

= 1.89V -20 ±1 +20 µA

Differential Internal

Termination Differential across RIN+ and RIN- 80 100 120 Ω

Resistance

SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD

DDT

= 100Ω

Serializer (Tx)

WORST CASE pattern 62 90

VDDn = 1.89V

VDDn Supply Current

(Figure 5)

PCLK = 43 MHz mA

(includes load

Default Registers

= 100Ω

current)

RANDOM PRBS-7 pattern

DDIOT

VDDIO = 1.89V

PCLK = 43 MHz 2 5

Serializer (Tx)

= 100Ω

Default Registers

VDDIO Supply

WORST CASE pattern mA

Current (includes load

VDDIO = 3.6V

(Figure 5)

current)

PCLK = 43 MHz 7 15

Default Registers

DDTZ

DDn

= 1.89V 370 775

Serializer (Tx) Supply PDB = 0V; All other

DDIOTZ

DDIO

= 1.89V 55 125 µA

Current Power-down LVCMOS Inputs = 0V

DDIO

= 3.6V 65 135

DDR

DDn

= 1.89V, C

= 8 pF PCLK = 43 MHz

Deserializer (Rx)

WORST CASE Pattern SSCG[3:0] = ON 60 96

VDDn Supply Current

(Figure 5) Default Registers

(includes load

DDn

= 1.89V, C

= 8 pF PCLK = 43 MHz

current)

RANDOM PRBS-7 Pattern Default Registers

DDIOR

DDIO

= 1.89V, C

= 8 pF

PCLK = 43 MHz

Deserializer (Rx)

WORST CASE Pattern 21 32

Default Registers

VDDIO Supply

(Figure 5)

Current (includes load

DDIO

= 3.6V, C

= 8 pF PCLK = 43 MHz

current)

49 83

WORST CASE Pattern Default Registers

DDRZ

DDn

= 1.89V 42 400

Deserializer (Rx)

PDB = 0V; All other

DDIORZ

Supply Current V

DDIO

= 1.89V 8 40 µA

LVCMOS Inputs = 0V

Power-down

DDIO

= 3.6V 350 800

Recommended Serializer Timing for PCLK

(1)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

TCP

Transmit Clock Period 23.3 T 100 ns

TCIH

Transmit Clock Input High

0.4T 0.5T 0.6T ns

Time

10 MHz – 43 MHz

TCIL

Transmit Clock Input Low

0.4T 0.5T 0.6T ns

Time

CLKT

PCLK Input Transition Time

0.5 3 ns

(Figure 11)

OSC

Internal oscillator clock

25 MHz

source

(1) Recommended Input Timing Requirements are input specifications and not tested in production.

DS90UB903Q-Q1, DS90UB904Q-Q1

ZHCSB32E –JUNE 2010–REVISED APRIL 2013

www.ti.com.cn

Serializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

LHT

CML Low-to-High Transition

= 100Ω (Figure 6) 150 330 ps

Time

HLT

CML High-to-Low Transition

= 100Ω (Figure 6) 150 330 ps

Time

DIS

Data Input Setup to PCLK 2.0 ns

Serializer Data Inputs (Figure 12)

DIH

Data Input Hold from PCLK 2.0 ns

PLD

Serializer PLL Lock Time R

= 100Ω

(1)(2)

1 2 ms

= 100Ω, PCLK = 10–43 MHz

6.386T 6.386T 6.386T

Serializer Delay Register 0x03h b[0] (TRFB = 1) ns

+ 5 + 12 + 19.7

(Figure 14)

JIND

Serializer output intrinsic deterministic

Serializer Output jitter . Measured (cycle-cycle) with

0.13 UI

Deterministic Jitter PRBS-7 test pattern

PCLK = 43 MHz

(3)(4)

JINR

Serializer output intrinsic random jitter

Serializer Output Random

(cycle-cycle). Alternating-1,0 pattern. 0.04 UI

Jitter

PCLK = 43 MHz

(3)(4)

JINT

Serializer output peak-to-peak jitter

includes deterministic jitter, random

Peak-to-peak Serializer jitter, and jitter transfer from serializer

0.396 UI

Output Jitter input. Measured (cycle-cycle) with

PRBS-7 test pattern.

PCLK = 43 MHz

(3)(4)

STXBW

Serializer Jitter Transfer PCLK = 43 MHz, Default Registers

1.90 MHz

Function -3 dB Bandwidth (Figure 20)

(3)

STX

Serializer Jitter Transfer PCLK = 43 MHz, Default Registers

0.944 dB

Function (Peaking) (Figure 20)

(3)

STXf

Serializer Jitter Transfer

PCLK = 43 MHz, Default Registers

Function (Peaking 500 kHz

(Figure 20)

(3)

Frequency)

(1) t

PLD

and t

DDLT

is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK

(2) Specification is ensured by design.

(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T

= +25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not ensured.

(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.

Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

RCP

Receiver Output Clock Period t

RCP

= t

TCP

PCLK 23.3 T 100 ns

PDC

Default Registers

PCLK Duty Cycle PCLK 45 50 55 %

SSCG[3:0] = OFF

LVCMOS Low-to-High Transition V

DDIO

: 1.71V to 1.89V or

CLH

1.3 2.0 2.8

Time 3.0 to 3.6V,

= 8 pF (lumped load) PCLK ns

CHL

LVCMOS High-to-Low Transition

Default Registers

1.3 2.0 2.8

Time

(Figure 16)

(1)

LVCMOS Low-to-High Transition V

DDIO

: 1.71V to 1.89V or

CLH

1.6 2.4 3.3

Time 3.0 to 3.6V,

Deserializer ROUTn

= 8 pF (lumped load) ns

CHL

Data Outputs

LVCMOS High-to-Low Transition

Default Registers

1.6 2.4 3.3

Time

(Figure 16)

(1)

ROS

ROUT Setup Data to PCLK V

DDIO

: 1.71V to 1.89V or 0.38T 0.5T

3.0V to 3.6V, Deserializer ROUTn

ROH

= 8 pF (lumped load) Data Outputs

ROUT Hold Data to PCLK 0.38T 0.5T

Default Registers

(1) Specification is ensured by characterization and is not tested in production.

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