ADuC7023：精密模拟微控制器与12位ADC技术规格

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"ADuC7023是一款由ADI公司制造的高性能模拟微控制器，结合了12位模拟输入/输出和ARM7TDMI核心的MCU。该器件具有增强型中断处理程序，适用于驱动软件工程师进行设计开发。DataSheet文档详细列出了其技术规格和功能特性。" ADuC7023是ADI公司推出的一款集成了高精度模拟电路和数字处理器的微控制器，主要特点包括： 1. **模拟输入/输出**：内置多通道12位ADC（模数转换器），最高采样速率可达1MSPS（百万样本每秒），支持多达12个通道，既可工作在全差分模式，也可在单端模式下运行。模拟输入范围从0V到VREF，提供广泛的信号处理能力。 2. **电压输出DAC**：包含4个12位电压输出数模转换器（DAC），这些输出可用于生成精确的电压信号，四个输出可供设计者灵活配置和使用。 3. **片上电压参考**：ADuC7023内置一个电压参考源，确保模拟信号处理的稳定性和精度。 4. **温度传感器**：集成的温度传感器可以实时监测系统的工作温度，有助于实现温度补偿或热管理。 5. **电压比较器**：该设备还包括一个电压比较器，可以用于比较两个电压信号，实现阈值检测等应用。 6. **微控制器单元**：基于ARM7TDMI内核，这是一种16位/32位精简指令集计算架构，提供高效能的数据处理能力。它支持JTAG端口，允许通过编程下载代码，便于调试和固件更新。 7. **中断处理**：增强型中断处理程序提高了系统的响应速度和实时性能，对于需要快速响应外部事件的应用尤其关键。 8. **知识产权保护**：ADI公司声明，提供的信息准确可靠，但不承担因使用信息导致的任何专利侵权或其他第三方权利侵犯的责任。同时，规格可能随时更改，无预先通知，并且没有默示许可任何ADI公司的专利或专利权。 9. **商标和版权**：ADuC7023及相关商标是ADI公司的财产，所有权利保留。用户应尊重并遵守相应的商标和版权法律。 ADuC7023因其集成度高、性能强大和灵活性强而广泛应用于各种领域，如工业控制、医疗设备、测试与测量以及通信系统等。通过详细阅读其DataSheet，软件工程师可以获得全面的技术参数、电气特性、引脚配置、操作指南等信息，以便于设计和实现高效的嵌入式系统。

ADuC7023 Data Sheet

Rev. C | Page 16 of 96

Pin No.

40-LFCSP 32-LFCSP Mnemonic Description

9 7 P0.4/IRQ0/SCL0/PLAI[0]/CONV General-Purpose Input and Output Port 0.4/External Interrupt Request

0//I

C0 Clock Signal/Programmable Logic Array Input Element 0/ADC

External Convert Start. By default, this pin is configured as a digital input

with a weak pull-up resistor enabled.

10 8 P0.5/SDA0/PLAI[1]/COMP

OUT

General-Purpose Input and Output Port 0.5/I

C0 Data Signal/Programmable

Logic Array Input Element 1/Voltage Comparator Output. By default, this

pin is configured as a digital input with a weak pull-up resistor enabled.

11 9 P0.6/MISO/SCL1/PLAI[2] General-Purpose Input and Output Port 0.6/SPI MISO Signal/I

C1 Clock On

32-Lead Package/Programmable Logic Array Input Element 2. By default,

this pin is configured as a digital input with a weak pull-up resistor

enabled.

12 10 P0.7/MOSI/SDA1/PLAO[0] General-Purpose Input and Output Port 0.7/SPI MOSI Signal/I

C1 Data

Signal On 32-Lead Package/Programmable Logic Array Output Element 0.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled.

21 17 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock

Generator Circuits. Connect to DGND if unused.

22 18 XCLKO Output from the Crystal Oscillator Inverter. Leave unconnected if unused.

16 N/A P1.7/PWM3/SDA1/PLAI[6] General-Purpose Input and Output Port 1.7/PWM Output 3/I

C Data

Signal/Programmable Logic Array Input Element 6. By default, this pin is

configured as a digital input with a weak pull-up resistor enabled.

15 N/A P1.6/PWM2/SCL1/PLAI[5] General-Purpose Input and Output Port 1.6/PWM Output 2/I

C Clock

Signal/Programmable Logic Array Input Element 5. By default, this pin is

configured as a digital input with a weak pull-up resistor enabled.

29 N/A P1.5/ADC6/PWM

TRIPINPUT

/PLAO[4] General-Purpose Input and Output Port 1.5/ADC Single-Ended or

Differential Analog Input 6/PWM

TRIPINPUT

/Programmable Logic Array Output

Element 4. By default, this pin is configured as a digital input with a weak

pull-up resistor enabled. When used as ADC input, the pull-up resistor

should be disabled manually.

7 N/A P1.4/ADC10/PLAO[3] General-Purpose Input and Output Port 1.4/ADC Single-Ended or

Differential Analog Input 10/Programmable Logic Array Output Element 3.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled. When used as ADC input, the pull-up resistor should be

disabled manually.

34 26 P1.3/ADC5/IRQ3/PLAI[4] General-Purpose Input and Output Port 1.3/ADC Single-Ended or

Differential Analog Input 5/External Interrupt Request 3/Programmable

Logic Array Input Element 4.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled. When used as ADC input, the pull-up resistor should be

disabled manually.

33 25 P1.2/ADC4/IRQ2/PLAI[3]/ECLK/ General-Purpose Input and Output Port 1.2/ADC Single-Ended or

Differential Analog Input 4/External Interrupt Request 2/Programmable

Logic Array Input Element 3/Input-Output for External Clock.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled. When used as ADC input, the pull-up resistor should be

disabled manually.

14 12 P1.1/

/IRQ1/PWM1/PLAO[2]/T1 General-Purpose Input and Output Port 1.1/SPI Interface Slave Select

(Active Low)/External Interrupt Request 1/PWM Output 1/Programmable

Logic Array Output Element 2/Timer 1 Input Clock. By default, this pin is

configured as a digital input with a weak pull-up resistor enabled.

P1.0/SCLK/PWM0/PLAO[1]

General-Purpose Input and Output Port 1.0/SPI Interface Clock Signal/

PWM Output 0/Programmable Logic Array Output Element 1. By default,

this pin is configured as a digital input with a weak pull-up resistor

enabled.

35 27 V

REF

2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor

when using the internal reference.

40 32 AGND Analog Ground. Ground reference point for the analog circuitry.

1 1 AV

3.3 V Analog Power.

Data Sheet ADuC7023

Rev. C | Page 19 of 96

OVERVIEW OF THE ARM7TDMI CORE

The ARM7® core is a 32-bit reduced instruction set computer

(RISC). It uses a single 32-bit bus for instruction and data. The

length of the data can be 8 bits, 16 bits, or 32 bits. The length of

the instruction word is 32 bits.

The ARM7TDMI is an ARM7 core with four additional features: T

support for the thumb (16-bit) instruction set, D support for

debug, M support for long multiplications, and I includes the

EmbeddedICE module to support embedded system debugging

THUMB MODE (T)

An ARM instruction is 32 bits long. The ARM7TDMI

processor supports a second instruction set that has been

compressed into 16 bits, called the Thumb® instruction set.

Faster execution from 16-bit memory and greater code density

can usually be achieved by using the Thumb instruction set

instead of the ARM instruction set, which makes the

ARM7TDMI core particularly suitable for embedded

applications.

However, the Thumb mode has two limitations. Thumb code

typically requires more instructions for the same job. As a

result, ARM code is usually best for maximizing the

performance of time critical code. Also, the Thumb instruction

set does not include some of the instructions needed for

exception handling, which automatically switches the core to

ARM code for exception handling.

See the ARM7TDMI user guide for details on the core

architecture, the programming model, and both the ARM

and ARM Thumb instruction sets.

LONG MULTIPLY (M)

The ARM7TDMI instruction set includes four extra instruc-

tions that perform 32-bit by 32-bit multiplication with a 64-bit

result, and 32-bit by 32-bit multiplication-accumulation (MAC)

with a 64-bit result. These results are achieved in fewer cycles

than required on a standard ARM7 core.

EmbeddedICE (I)

EmbeddedICE provides integrated on-chip support for the core.

The EmbeddedICE module contains the breakpoint and watch-

point registers that allow code to be halted for debugging purposes.

These registers are controlled through the JTAG test port.

When a breakpoint or watchpoint is encountered, the processor

halts and enters debug state. Once in a debug state, the

processor registers can be inspected as well as the Flash/EE,

SRAM, and memory mapped registers.

EXCEPTIONS

ARM supports five types of exceptions and a privileged

processing mode for each type. The five types of exceptions are:

• Normal interrupt or IRQ. This is provided to service

general-purpose interrupt handling of internal and

external events.

• Fast interrupt or FIQ. This is provided to service data

transfers or communication channels with low latency. FIQ

has priority over IRQ.

• Memory abort.

• Attempted execution of an undefined instruction.

• Software interrupt instruction (SWI). This can be used to

make a call to an operating system.

Typically, the programmer defines interrupt as IRQ, but for

higher priority interrupt, that is, faster response time, the

programmer can define interrupt as FIQ.

ARM REGISTERS

ARM7TDMI has a total of 37 registers: 31 general-purpose

registers and six status registers. Each operating mode has

dedicated banked registers.

When writing user-level programs, 15 general-purpose 32-bit

registers (R0 to R14), the program counter (R15), and the

current program status register (CPSR) are usable. The

remaining registers are only used for system-level programming

and exception handling.

When an exception occurs, some of the standard registers are

replaced with registers specific to the exception mode. All excep-

tion modes have replacement banked registers for the stack

pointer (R13) and the link register (R14) as represented in

Figure 14. The fast interrupt mode has more registers (R8 to R12)

for fast interrupt processing. This means the interrupt processing

can begin without the need to save or restore these registers,

and thus save critical time in the interrupt handling process.

08675-008

USABLE IN USER MODE

SYSTEM MODES ONLY

SPSR_UND

SPSR_IRQ

SPSR_ABT

SPSR_SVC

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

R13_UND

R14_UND

R10

R11

R12

R13

R14

R15 (PC)

R13_IRQ

R14_IRQ

R13_ABT

R14_ABT

R13_SVC

R14_SVC

SPSR_FIQ

CPSR

USER MODE

FIQ

MODE

SVC

MODE

ABORT

MODE

IRQ

MODE

UNDEFINED

MODE

Figure 14. Register Organization

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