VSP5610
VSP5611
VSP5612
www.ti.com.cn
ZHCS260 –JUNE 2011
ELECTRICAL CHARACTERISTICS: VSP5612
All specifications at T
A
= +25°C, supply voltage = +3.3 V, conversion rate = 17.5 MHz, and four-channel mode, unless
otherwise noted.
VSP5612
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Allowable input voltage 0 VDD V
Full-scale range Gain = 1 V/V 1 V
PP
Input capacitor 5 pF
DIGITAL INPUT
Positive-going threshold V
T+
DVDD_IO × 0.7 V
Negative-going threshold V
T–
DVDD_IO × 0.3 V
Hysteresis (V
T+
– V
T–
) ΔV
T
DVDD_IO × 0.13 V
Input current I
IN
±1 µA
Input capacitor 5 pF
DIGITAL OUTPUT
I
OH
= –2 mA DVDD_IO – 0.45 V
High-level output voltage V
OH
I
OH
= –4 mA DVDD_IO – 0.50 V
I
OH
= –8 mA DVDD_IO – 0.50 V
I
OL
= 2 mA 0.35 V
Low-level output voltage V
OL
I
OL
= 4 mA 0.50 V
I
OL
= 8 mA 0.65 V
XP1, XP2, XP3, XP4 –1 1 ns
TG output timing skew
Other signals –2 2 ns
CMOS data output bit rate 80 MHz
LVDS DRIVER (TA, TB, TC, TCLK)
Differential steady-state output
|V
OD
| R
L
= 100 Ω 300 350 400 mV
voltage adjustment range
Differential steady-state output
|V
OD
| 3 Steps
adjustment step
Differential steady-state output
|V
OD
| –30 30 %
voltage tolerance
Change in the steady-state
differential output voltage magnitude Δ|V
OD
| 35 mV
between opposite binary states
Steady-state common-mode output
V
OC(SS)
R
L
= 100 Ω 1.125 1.375 V
voltage
Peak-to-peak common-mode output
V
OC(PP)
80 150 mV
voltage
Short-circuit output current I
OS
V
O
= 0 V (V
O
= TA, TB, TC, TCLK) –6 ±24 mA
V
O
= 0 V to LVDD
Hi-Z output current I
OZ
±10 µA
(V
O
= TA, TB, TC, TCLK)
Transition time, differential output
t
LR
/t
LF
0.75 1.5 ns
voltage
TCLK clock rate 8 70 MHz
LVDS RECEIVER (RCLK)
Positive-going differential input
V
IT+
100 mV
threshold voltage
Negative-going differential input
V
IT–
–100 mV
threshold voltage
RCLK clock rate 1 23.33 MHz
Copyright © 2011, Texas Instruments Incorporated 9
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