XAPP859: Virtex-5 FPGA DMA参考设计与Endpoint Block Plus

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"XAPP859开发文档是Xilinx公司发布的一个应用笔记，主要针对Virtex-5 FPGA的LogiCORE™ Endpoint Block Plus进行详细的设计说明，专注于使用endpoint发起的直接内存访问（DMA）数据传输。该文档适用于硬件平台ML555，并利用板载的DDR2内存来存储DMA数据。同时，设计也可以适应ML505平台，展示1-lane endpoint设计的DMA性能。" 在XAPP859(v1.1)中，主要内容涵盖了以下几个关键知识点： 1. **Endpoint Block Plus for Virtex-5 FPGAs**：这是Xilinx为Virtex-5系列FPGA提供的一个核心模块，用于实现PCI Express（PCIe）接口中的endpoint功能。Endpoint Block Plus支持endpoint设备的数据传输，可以作为一个从设备接收主机的命令并响应。 2. **DMA（Direct Memory Access）数据传输**：DMA是一种允许外围设备直接与系统内存交换数据的技术，无需CPU的介入。在XAPP859中，设计展示了如何构建一个8-lane的endpoint设计，通过DDR2内存接口进行DMA数据传输。 3. **ML555硬件平台**：此设计是面向ML555开发板进行优化的，该板载有Virtex-5 FPGA和DDR2内存，用于实际实现和测试DMA功能。 4. **DDR2内存**：作为数据存储媒介，DDR2内存被用于存储DMA操作中的数据。设计说明了如何将DDR2接口集成到endpoint设计中，以便高效地处理高速数据流。 5. **1-lane DMA性能评估**：除了在ML555平台上实现8-lane设计，设计还可在ML505平台上运行，展示1-lane endpoint的DMA性能，这有助于理解不同lane配置对性能的影响。 6. **驱动程序与GUI应用程序**：Xilinx提供了驱动程序和图形用户界面（GUI）工具，用于在主机PC上分配和初始化系统内存缓冲区，并设置DMA传输。这些工具简化了用户与设计的交互，使配置和测试变得更加直观。 7. **交易层包（Transaction Layer Packets, TLPs）**：设计演示了如何在DMA模式下发送和接收TLPs，作为DMA发起者，以及如何响应目标交易，这表明了设计能够完全参与PCIe协议的交易过程。 8. **中断（Interrupts）**：文档可能还涉及中断机制，这是PCIe通信中一个重要的部分，用于通知主机设备完成特定操作或需要处理的事件。 XAPP859对于那些想要实现PCIe endpoint应用，特别是涉及高性能、低延迟DMA传输的开发者来说，是一份非常有价值的参考资料。它不仅提供了具体的设计实现步骤，还包括了必要的软件支持，使得开发者可以快速理解和部署基于Virtex-5 FPGA的PCIe endpoint解决方案。

Reference System

XAPP859 (v1.1) July 31, 2008 www.xilinx.com 11

Non-Posted Packet Generator

The non-posted packet generator accepts read DMA requests from the DMA Control/Status

DMA transaction. These headers are placed into a small FIFO to be read by the TX TRN state

machine block. Two main logical blocks make up the non-posted packet generator:

• Non-posted packet slicer

• Non-posted packet builder

The non-posted packet slicer block accepts read DMA requests from the DMA Control/Status

rules set forth in the PCI Express Base Specification [Ref 4]. Essentially, the non-posted packet

slicer breaks up read DMA requests based on these rules:

• Requested data payload length does not exceed the Max_Read_Request_Size field of the

device control register.

• Address/length combinations cannot cross a 4 KB address boundary.

The non-posted packet generator block passes the length (length[9:0]) and source address

(dmaras_reg[63:0]) fields to the non-posted packet builder block, using a simple handshaking

protocol (go/ack signals). Source and destination addresses must be aligned on 128-byte

address boundaries. The non-posted packet generator block is designed to take advantage of

all possible Max_Read_Request_Size values and can accept transfer size inputs

(dmarxs[31:0]) of 128, 256, 512, 1024, 2048, and 4096 bytes.

The non-posted packet builder block builds non-posted memory read request packet headers,

and then writes the headers into a small 64 x 64 CORE Generator software FIFO built with

distributed RAM. Also, this block is capable of dynamically generating 3DW or 4DW headers

based on the source address (dmaras[63:0]) input. If dmaras[63:32] is zero, a 3DW header is

built; otherwise, a 4DW header is built. Figure 13 shows a 3DW and 4DW posted memory read

packet header.

FirstBE[3:0] First DWORD byte enable field. Always 1111 for this design because

memory writes are always more than one DWORD in length.

Address[63:32] Upper 32-bit host memory address for 64-bit systems using memory above

4 GB. If the host processor writes a non-zero value to the DMAWAD_U

64-bit addressing and 4DW TLP packet headers.

Address[31:0] Lower 32-bit host memory address for 32-bit systems or 64-bit systems

using memory below 4 GB.

Table 1: Posted Memory Write Header Field Information (Cont’d)

Header Field Description

Reference System

XAPP859 (v1.1) July 31, 2008 www.xilinx.com 12

Table 2 describes the non-posted memory read header fields.

The non-posted packet builder block also provides some information to the RX engine so that

the RX engine can qualify the resulting incoming completion packets from the non-posted

memory read request packets and place the data payload in the correct DDR2 memory

X-Ref Target - Figure 13

Figure 13: 3DW and 4DW Non-Posted Memory Read Packet Headers

Address [31:2] 00

Address [63:32]

Requester ID Tag

31 302928 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210

Last DW BE First DW BE

Length0000000000010 0 0 AttrEPTDTC

Address [31:2] 00

Requester ID

+0 +1 +2 +3

Memory Read 3DW Header Overview

Memory Read 4DW Header Overview

Tag

31 302928 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210

Last DW BE First DW BE

Length0000000000000 0 0 AttrEPTDTC

X859_13_040908

Table 2: Non-Posted Memory Read Header Field Information

Header Field Description

TC[2:0] Traffic class field. Always 000 for this design.

TD TLP digest bit. Always 0. Design does not implement ECRC.

EP Poisoned bit. Always 0. Not used in this design.

ATTR[1:0] Attributes field. Always 10 for memory reads. The relaxed ordering bit

must be set to comply with the requirements of using the completion

streaming mode. Refer to the LogiCORE Endpoint Block Plus for PCI

Express User Guide [Ref 2] for more details.

Length[9:0] Length of data payload in DWORDS. This field is provided by the

non-posted packet slicer block.

Requester ID[15:0] Requester ID field. This is provided by the Endpoint Block Plus wrapper

for PCI Express.

Tag[7:0] Tag field. A unique tag provided by tag generator block.

LastBE[3:0] Last DWORD byte enable field. Always 1111 for this design because

memory reads are aligned on 128-byte address boundaries.

FirstBE[3:0] First DWORD byte enable field. Always 1111 for this design because

memory reads are always more than one DWORD in length.

Address[63:32] Upper 32-bit host memory address for 64-bit systems using memory

above 4 GB. If the host processor writes a non-zero value to the

DMARAS_U register in the DMA Control/Status Register File (Ta ble 3),

the design uses 64 bit addressing and 4DW TLP packet headers.

Address[31:0] Lower 32-bit host memory address for 32-bit systems or 64-bit systems

using memory below 4 GB.

Reference System

XAPP859 (v1.1) July 31, 2008 www.xilinx.com 13

address. This information is provided to the RX engine through a small buffer called the read

request RAM. For more information on this FIFO, refer to “Read Request Wrapper,” page 20.

Completer Packet Generator

The completer packet generator accepts memory read requests from the RX engine and

generates completer packet headers. These headers are placed into a small FIFO to be read

by the TX TRN state machine block.

Tag Generator

The tag generator block generates unique tags upon request from the posted (not required)

and non-posted (required) packet generator blocks. The tags are generated from a simple 5-bit

counter that rolls over to zero upon reaching its maximum value. The extended tag function is

not supported by this reference design. Simple arbitration logic grants access to the tag counter

between the posted and non-posted packet generator blocks.

Transmit TRN State Machine

The transmit TRN state machine block sends packets to the TX TRN interface of the Endpoint

Block Plus wrapper. The transmit TRN state machine block loads header information from

packet generator FIFOs. The 64-bit data is sourced from the egress data presenter block for

posted memory writes (and completer packets). The state machine and datapath pipeline are

clock enabled by the trn_tdst_rdy_n signal from the Endpoint Plus block wrapper. When

deasserted, this signal signifies that the Endpoint Plus block wrapper is not ready to receive

packet headers or data, and must immediately stop transmission to the TX TRN interface. The

state machine and datapath are also clock enabled by a data_stall signal from the DMA-to-

DDR2 interface block. This signal is asserted if the DMA-to-DDR2 interface temporarily runs

out of data provided to the egress data presenter block, which is possible if a DDR2 memory

refresh cycle occurs in the middle of data transmission. The transmit TRN state machine block

is also responsible for signaling to the DMA Control/Status Register File when a write DMA

transaction is complete.

RX Engine

The RX engine receives packets from the Endpoint Block Plus wrapper RX TRN interface and

routes the data payload to the correct memory address. The RX engine is informed of pending

read requests from the TX engine through the read request wrapper. Supported packet types

are completions, memory reads, and memory writes. This reference design does not provide

an I/O BAR function, so I/O packets are filtered by the Endpoint Block Plus wrapper. Message

packets are filtered by the RX engine. Figure 14 shows a block diagram of the RX engine.

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