AXI桥接PCIe Gen3子系统v3.0设计指南

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AXI Bridge for PCI Express Gen3 Subsystem v3.0 是一款专为高性能计算和数据传输设计的IP核心，旨在连接Advanced eXtensible Interface (AXI)总线与下一代PCI Express (PCIe) Gen3标准，以实现系统内部的高速通信。这款产品是基于Vivado Design Suite的PG194版本，发布于2023年11月24日，由AMD Adaptive Computing开发，致力于创造一个包容性的工作环境。该产品的特点包括支持PCIe Gen3的多种交易类型和功能，如差分信号、错误校验机制以及高级配置/状态交换(CAS)。然而，需要注意的是，它可能存在一些不支持的功能和局限性，比如特定的PCIe能力可能在某些配置下不可用。此外，设计时要考虑PCIe交易类型的兼容性和PCIe规范的要求，例如数据速率、带宽和时序约束。对于接口规范，该桥接器符合相关PCIe标准，确保了系统的兼容性和互操作性。性能和资源利用方面，产品强调了高效的数据传输速率和对设计者硬件资源的优化管理。对于最小设备要求，用户需要确保其系统具备足够的AXI控制器和PCIe端口来充分利用这款IP。产品规格部分详细列出了接口描述、桥接参数以及内存映射，设计者在集成时需要遵循这些指南。设计流程涉及选择合适的桥接配置，理解不同端口的功能划分，并根据实际应用调整参数以满足性能需求。此外，AMD已启动内部项目，以消除产品和相关文档中的非包容性语言，这反映了公司对于创建无偏见环境的决心。尽管早期产品可能仍存在此类问题，但AMD正在积极更新以适应不断发展的行业标准。用户在参考文档时，应关注任何关于语言和术语变化的后续通知。 AXI Bridge for PCI Express Gen3 Subsystem v3.0是一个关键的工具，帮助设计师构建高效、兼容的系统架构，同时需关注其最新的产品更新和语言政策，以确保设计的现代性和可接受性。

Table 3: Global Signals (cont'd)

Signal Name I/O Description

interrupt_out_msi_vec0to31 O Interrupt signal. It is asserted for as long as there

exists at least one bit asserted in the Root Port MSI

Interrupt Decode 1 register and is not masked in

the Root Port MSI Interrupt Decode 1 Mask

Only available in Root Port configuration with

Interrupt Decode mode

interrupt_out_msi_vec32to63

O Interrupt signal. It is asserted for as long as there

exists at least one bit asserted in the Root Port MSI

Interrupt Decode 2 register and is not masked in

the Root Port MSI Interrupt Decode 2 Mask

Only available in Root Port configuration with

Interrupt Decode mode.

axi_aresetn O

AXI Bridge for PCIe Gen3: Reset signal for the S_AXI

and M_AXI interfaces. axi_aresetn deasserts after a

function has transitioned into D0_active power

state (configured and enabled).

DMA/Bridge Subsystem for PCIe in AXI Bridge

mode:

In Endpoint configuration, reset signal for the

S_AXIB and M_AXIB interfaces. axi_aresetn

deasserts after a function has transitioned into

D0_active power state (configured and enabled).

In Root Port configuration, axi_aresetn deasserts

after GT transceivers are initialized (assertion of

Phy Ready, independent from PCIe link status).

IMPORTANT! The default value of this pin in the

DMA/Bridge Subsystem for PCIe in AXI Bridge mode

has changed as mentioned above.

axi_ctl_aresetn O

AXI Bridge for PCIe Gen3: Reset signal for the

S_AXI_CTL interface. axi_ctl_aresetn deasserts after

two axi_ctl_aclk (or axi_aclk for newer IP that does

not have the axi_ctl_aresetn pin) cycles after

sys_rst_n deasserts.

DMA/Bridge Subsystem for PCIe in AXI Bridge

mode: Reset signal for the S_AXIL interface. In

Endpoint configuration, axi_ctl_aresetn deasserts

after a function has transitioned into D0_active

power state (configured and enabled). In Root Port

configuration, axi_ctl_aresetn deasserts after GT

transceivers are initialized (assertion of Phy Ready,

independent from PCIe link status).

IMPORTANT! The default value of this pin in the

DMA/Bridge Subsystem for PCIe in AXI Bridge mode

has changed as mentioned above.

Chapter 3: Product Specification

PG194 (v3.0) November 24, 2023

AXI Bridge for PCI Express Gen3 Subsystem 16

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Table 3: Global Signals (cont'd)

Signal Name I/O Description

dma_bridge_resetn I

Optional pin available to DMA/Bridge Subsystem

for PCIe in AXI Bridge mode only and appears only

when SOFT_RESET_EN parameter is set to TRUE.

This pin is intended to be user driven reset when

link down, Function Level Reset, Dynamic Function

eXchange, or another error condition defined by

user has occurred. It is not required to be toggled

during initial link up operation.

When used, all PCIe traffic must be in quiesce state.

The signal must be asserted for longer than the

Completion Timeout value (typically 50 ms).

0: Resets all internal Bridge engines and registers

as well as asserts axi_aresetn and axi_ctl_aresetn

signals while maintaining PCIe link up.

1: Normal operation.

AXI Slave Interface

For all signals in this interface, s_axi_* is used for the AXI Bridge for PCIe Gen3 core, and

s_axib_* is used for the DMA/Bridge Subsystem for PCIe in AXI Bridge mode.

Table 4: AXI Slave Interface Signals

Signal Name I/O Description

s_axi(b)_awid[c_s_axi_id_width-1:0] I Slave write address ID

s_axi(b)_awaddr[axi_addr_width-1:0] I Slave write address

s_axi(b)_awregion[3:0] I Slave write region decode

s_axi(b)_awlen[7:0] I Slave write burst length

s_axi(b)_awsize[2:0] I Slave write burst size

s_axi(b)_awburst[1:0] I Slave write burst type

s_axi(b)_awvalid I Slave address write valid

s_axi(b)_awready O Slave address write ready

s_axi(b)_wdata[axi_data_width-1:0] I Slave write data

s_axi(b)_wstrb[axi_data_width/8-1:0] I Slave write strobe

s_axi(b)_wlast I Slave write last

s_axi(b)_wvalid I Slave write valid

s_axi(b)_wready O Slave write ready

s_axi(b)_wuser I

Reserved. Tie to GND.

Note: This signal is disabled for AXI Bridge for PCI

Express Gen3. This signal is also disabled for the

DMA/Bridge Subsystem for PCIe in AXI Bridge

mode unless CONFIG.parity_settings =

Propagate_Parity is set.

s_axi(b)_bid[c_s_axi_id_width-1:0]

O Slave response ID

s_axi(b)_bresp[1:0] O Slave write response

Chapter 3: Product Specification

PG194 (v3.0) November 24, 2023

AXI Bridge for PCI Express Gen3 Subsystem 17

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Table 5: AXI Master Interface Signals (cont'd)

Signal Name I/O Description

m_axi(b)_awsize[2:0] O

Master write burst size

All write requests show the requested size is equal

to the Master AXI data width except for 1DW

request. 1DW request is supported as a special

case. As an example, if the IP is configured for 128-

bit Master AXI data width,m_axi(b)_awsize[2:0] will

show '2' for 1DW request and '4' for 2DW request

instead of '3'.

Write data must be further masked with

m_axi(b)_wstrb signal which will indicates valid byte

lanes to avoid writing to disabled byte lanes.

The IP doesn't support narrow burst on Master

Interface. The above case of 'narrow transfer' is

only for single beat transaction.

m_axi(b)_awburst[1:0]

O Master write burst type

m_axi(b)_awprot[2:0] O Master write protection type

m_axi(b)_awvalid O Master write address valid

m_axi(b)_awready I Master write address ready

m_axi(b)_wdata[axi_data_width-1:0] O Master write data

m_axi(b)_wstrb[axi_data_width/8-1:0] O Master write strobe

m_axi(b)_wlast O Master write last

m_axi(b)_wvalid O Master write valid

m_axi(b)_wready I Master write ready

m_axi(b)_wuser O

Reserved. Internally tied to GND.

Note: This signal is disabled for AXI Bridge for PCI

Express Gen3. This signal is also disabled for the

DMA/Bridge Subsystem for PCIe in AXI Bridge

mode unless CONFIG.parity_settings =

Propagate_Parity is set.

m_axi(b)_bresp[1:0]

I Master write response

m_axi(b)_bvalid I Master write response valid

m_axi(b)_bready O Master response ready

m_axi(b)_araddr[axi_addr_width-1:0] O Master read address

m_axi(b)_arlen[7:0] O Master read burst length

m_axi(b)_arsize[2:0] O

Master read burst size

All read requests show the requested size is equal

to the Master AXI data width except for 1DW

request. 1DW request is supported as a special

case. As an example, if the IP is configured for 128-

bit Master AXI data width, this signal will show '2'

for 1DW request and '4' for 2DW request instead of

'3'. This behavior can be ignored if the request is

not doing destructive reads; precaution must be

taken for destructive register reads.

The IP does not support narrow burst on Master

Interface. The above case of narrow transfer is only

for single beat transaction.

m_axi(b)_arburst[1:0]

O Master read burst type

m_axi(b)_arprot[2:0] O Master read protection type

Chapter 3: Product Specification

PG194 (v3.0) November 24, 2023

AXI Bridge for PCI Express Gen3 Subsystem 19

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Table 5: AXI Master Interface Signals (cont'd)

Signal Name I/O Description

m_axi(b)_arvalid O Master read address valid

m_axi(b)_arready I

Master read address ready. This signal only

responds when Bus Master Enable bit is set in the

Command register within the PCI

Configuration

Space.

m_axi(b)_rdata[axi_data_width-1:0] I Master read data

m_axi(b)_rresp[1:0] I Master read response

m_axi(b)_rlast I Master read last

m_axi(b)_rvalid I Master read valid

m_axi(b)_rready O Master read ready

m_axi(b)_ruser I

Reserved. Tie to GND.

Note: This signal is disabled for AXI Bridge for PCI

Express Gen3. This signal is also disabled for the

DMA/Bridge Subsystem for PCIe in AXI Bridge

mode unless CONFIG.parity_settings =

Propagate_Parity is set.

AXI4-Lite Control Interface

For all signals in this interface, s_axi_ctl* is used for the AXI Bridge for PCIe Gen3 core, and

s_axil_* is used for the DMA/Bridge Subsystem for PCIe in AXI Bridge mode.

Table 6: AXI4-Lite Control Interface Signals

Signal Name I/O Description

Endpoint configuration: s_axi_ctl_awaddr[11:0] |

s_axil_awaddr[31:0]

Root Port configuration: s_axi_ctl_awaddr[27:0] |

s_axil_awaddr[31:0]

Slave write address.

For DMA/Bridge Subsystem for PCIe in AXI Bridge

mode, address must always be 512 MB aligned.

s_axil_awaddr[28] = 1'b0 selects Bridge Register

Memory Map and Enhanced Configuration Access

Memory Map.

s_axil_awaddr[28] = 1'b1 selects DMA/Bridge

Subsystem for PCIe Register Memory Map.

For AXI Bridge for PCIe Gen3 core, address must be

aligned to 4 KB in Endpoint configuration and 256

MB in Root Port configuration.

s_axi_ctl_awvalid | s_axil_awvalid

I Slave write address valid

s_axi_ctl_awready | s_axil_awready O Slave write address ready

s_axi_ctl_wdata[31:0] | s_axil_wdata[31:0] I Slave write data

s_axi_ctl_wstrb[3:0] | s_axil_wstrb[3:0] I Slave write strobe

s_axi_ctl_wvalid | s_axil_wvalid I Slave write valid

s_axi_ctl_wready | s_axil_wready O Slave write ready

s_axi_ctl_bresp[1:0] | s_axil_bresp[1:0] O Slave write response

s_axi_ctl_bvalid | s_axil_bvalid O Slave write response valid

Chapter 3: Product Specification

PG194 (v3.0) November 24, 2023

AXI Bridge for PCI Express Gen3 Subsystem 20

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