NXP LPC17xx 系列 Cortex-M3 MCU 用户手册

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"LPC17xx系列用户手册，包括LPC1758/56/54/52/51，是NXP公司基于Cortex-M3内核的微控制器的详细文档，涵盖了从LPC1769到LPC1751的所有型号。这份用户手册提供了一系列关键功能的介绍，如32位处理能力、USB、以太网、CAN总线、I2S接口等。" NXP的LPC17xx系列微控制器是基于高效的Cortex-M3内核设计的，这个系列包括多个型号，如LPC1758、LPC1756、LPC1754、LPC1752和LPC1751，它们都具有丰富的外设集和强大的处理性能。这些器件广泛应用于各种嵌入式系统，因其32位处理能力和低功耗特性而受到青睐。手册中的内容详尽地介绍了每个型号的特性和使用方法。例如，LPC17xx系列微控制器支持USB（通用串行总线）接口，这使得它们能够轻松连接到各种外部设备，如键盘、鼠标或存储设备。同时，内置的以太网接口则提供了网络通信的能力，适用于需要联网的IoT（物联网）应用。此外，手册还涉及了CAN（控制器局域网络）总线，这是一种在汽车电子和工业自动化领域广泛应用的通信协议。LPC17xx系列的CAN接口允许设备之间高效且可靠的通信，适合在需要实时性和稳定性高的环境中使用。 I2S（集成电路间声音）接口在音频应用中十分常见，使得LPC17xx能与音频编解码器和其他数字音频设备无缝配合，实现高质量的音频处理。手册的修订历史部分提到，LPC1758、LPC1767和LPC1768在后期版本中被添加到关键词列表和部分识别号表中，表明手册不断更新以包含更多新的产品信息。值得注意的是，关于DMA（直接内存访问）在睡眠模式下的操作说明在某个版本中被移除，可能是因为有更具体的指导或者该功能在某些条件下不再适用。在硬件资源方面，手册还会详细介绍时钟管理，如CLKOUT功能的移除可能意味着在某些更新的模型中，这个特定的时钟输出不再可用，开发者需要参考最新的资料来规划时钟配置。总体来说，"LPC17xx用户手册"是开发人员和工程师全面了解和利用NXP LPC17xx系列微控制器的关键参考资料，它提供了深入的技术细节，帮助用户充分利用这些MCU的潜能，进行高效和可靠的系统设计。

User manual Rev. 01 — 4 January 2010 16 of 835

NXP Semiconductors

UM10360

Chapter 2: LPC17xx Memory map

6. Bus fault exceptions

The LPC17xx generates Bus Fault exception if an access is attempted for an address that

is in a reserved or unassigned address region. The regions are areas of the memory map

that are not implemented for a specific derivative. These include all spaces marked

“reserved” in Figure 2–3

For these areas, both attempted data access and instruction fetch generate an exception.

In addition, a Bus Fault exception is generated for any instruction fetch that maps to an

AHB or APB peripheral address.

Within the address space of an existing APB peripheral, an exception is not generated in

response to an access to an undefined address. Address decoding within each peripheral

is limited to that needed to distinguish defined registers within the peripheral itself. For

example, an access to address 0x4000 D000 (an undefined address within the UART0

space) may result in an access to the register defined at address 0x4000 C000. Details of

such address aliasing within a peripheral space are not defined in the LPC17xx

documentation and are not a supported feature.

If software executes a write directly to the flash memory, the flash accelerator will

generate a Bus Fault exception. Flash programming must be accomplished by using the

specified flash programming interface provided by the Boot Code.

Note that the Cortex-M3 core stores the exception flag along with the associated

instruction in the pipeline and processes the exception only if an attempt is made to

execute the instruction fetched from the disallowed address. This prevents accidental

aborts that could be caused by prefetches that occur when code is executed very near a

memory boundary.

User manual Rev. 01 — 4 January 2010 19 of 835

NXP Semiconductors

UM10360

Chapter 3: LPC17xx System control

On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset,

External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time

(maximum of 60 μs on power-up) and after the IRC provides a stable clock output, the

reset signal is latched and synchronized on the IRC clock. Then the following two

sequences start simultaneously:

1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is

de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times

out. The boot code performs the boot tasks and may jump to the flash. If the flash is

not ready to access, the Flash Accelerator will insert wait cycles until the flash is

ready.

2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is

de-asserted. The flash wakeup-timer generates the 100 μs flash start-up time. Once it

times out, the flash initialization sequence is started, which takes about 250 cycles.

When it’s done, the Flash Accelerator will be granted access to the flash.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

Figure 3–5

shows an example of the relationship between the RESET, the IRC, and the

processor status when the LPC17xx starts up after reset. See Section 4–3.2 “

Main

oscillator” for start-up of the main oscillator if selected by the user code.

Fig 4. Reset block diagram including the wake-up timer

APB read of

PDBIT

in PCON

power-down

OSC

to other

blocks

WAKE-UP TIMER

watchdog

reset

external

reset

START

COUNT 2

internal RC

oscillator

Reset to the

on-chip circuitry

Reset to

PCON.PD

write “1”

from APB

reset

EINT0 wake-up

EINT1 wake-up

EINT2 wake-up

POR

BOD

EINT3 wake-up

RTC wake-up

BOD wake-up

Ethernet MAC wake-up

USB need_clk wake-up

CAN wake-up

GPIO0 port wake-up

GPIO2 port wake-up

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