MAX517/MAX518/MAX519: 串行D/A转换器的C语言应用与特性详解

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MAX517-MAX5是一系列8位电压输出数字模拟转换器（DACs），它们具有独特的2线串行接口设计，能够实现多设备间的高效通信。这些器件支持单个5V电源供电，并配备精密缓冲器，使输出电压能够达到电源极性范围（即轨对轨）。MAX517作为单通道DAC，而MAX518和MAX519则是双通道版本，分别提供单一或独立的参考输入。 MAX517/MAX518/MAX519的关键特性在于其内置的软件协议，使得数据传输速率最高可达400kbps。通过双缓冲输入配置，用户可以单独或同时更新双设备的DAC寄存器，提高了灵活性。此外，这些设备还具备低功耗模式，当处于休眠状态时，电源电流降至4μA，大大节省能源。在上电时，电源-on-reset功能确保输出电压初始为0V，便于系统的初始化。在封装形式上，MAX517和MAX518提供了紧凑的8针DIP和SO封装，便于集成到各种应用中，而MAX519则可能采用不同的封装类型，以满足更广泛的应用需求。MAX517-MAX5系列是为需要高精度、低成本和简单接口的系统设计者提供了理想的解决方案，无论是单通道还是双通道的模拟信号生成，都能轻松实现数字化控制。

MAX517/MAX518/MAX519

2-Wire Serial 8-Bit DACs with

Rail-to-Rail Outputs

4 _______________________________________________________________________________________

Note 1: For the MAX518 (full-scale = V

) the last three codes are excluded from the TUE and DNL specifications, due to the limited

output swing when loaded with 10kΩ to GND.

Note 2: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.

Note 3: Input capacitance is code dependent. The highest input capacitance occurs at code FF hex.

Note 4: V

REF_

= 4V

P-P

, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the

code of all other DACs to 00 hex.

Note 5: V

REF_

= 4Vp-p, 10kHz, DAC code = 00 hex.

Note 6: Guaranteed by design.

Note 7: I

C compatible mode. R

PULLUP

= 1.7kΩ.

Note 8: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.

Note 9: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V

of the SCL signal) in order to

bridge the undefined region of SCL’s falling edge.

Note 10: Cb = total capacitance of one bus line in pF. t

and t

measured between 0.3V

and 0.7V

Note 11: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

Hold Time, (Repeated) Start Condition t

HD, STA

0.6 µs

Low Period of the SCL Clock t

LOW

1.3 µs

High Period of the SCL Clock t

HIGH

0.6

PARAMETER SYMBOL MIN TYP MAX UNITS

Serial Clock Frequency f

SCL

0400kHz

Bus Free Time Between a STOP and a

START Condition

BUF

1.3 µs

CONDITIONS

µs

Setup Time for a Repeated START Condition t

SU, STA

0.6 µs

Data Hold Time t

HD, DAT

0 0.9 µs

Data Setup Time t

SU, DAT

100

(Note 9)

Fall Time of SDA Transmitting t

20 + 0.1Cb 250 ns

Setup Time for STOP Condition t

SU, STO

0.6 µs

Capacitive Load for Each Bus Line Cb 400

SINK

≤ 6mA (Notes 7, 10)

Rise Time of Both SDA and SCL Signals, Receiving t

20 + 0.1Cb 300 ns

Fall Time of Both SDA and SCL Signals, Receiving t

20 + 0.1Cb 300

(Note 10)

(Note 10) ns

Pulse Width of Spike Suppressed t

050(Notes 6, 11) ns

TIMING CHARACTERISTICS

= 5V ±10%, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are T

= +25°C.)

ELECTRICAL CHARACTERISTICS (continued)

= 5V ±10%, V

REF_

= 4V (MAX517, MAX519), R

= 10kΩ, C

= 100pF, T

= T

MIN

to T

MAX

, unless otherwise noted.

Typical values are T

= +25°C.)

PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS

Digital-Analog Glitch Impulse 12Code 128 to 127 nV-s

Signal to Noise + Distortion

Ratio (MAX517, MAX519)

SINAD 87

REF_

= 4Vp-p at 1kHz, V

= 5V,

Code = FF hex

Multiplying Bandwidth

(MAX517, MAX519)

1 MHz

Wideband Amplifier Noise 60 µV

RMS

Supply Voltage V

4.5 5.5 V

1.5 3.0

MAX517E/M

MAX517C

2.5 5

1.5 3.5

REF_

= 4Vp-p, 3dB bandwidth

Supply Current

Normal mode, output(s)

unloaded, all digital inputs

at 0V or V

2.5 6

MAX518C, MAX519C

MAX518E/M, MAX519E/M

Power-down mode 420µA

POWER REQUIREMENTS

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