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16
SLAU356I–March 2015–Revised June 2019
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Copyright © 2015–2019, Texas Instruments Incorporated
Contents
25.3.2 Character Format ............................................................................................... 937
25.3.3 Master Mode .................................................................................................... 937
25.3.4 Slave Mode...................................................................................................... 938
25.3.5 SPI Enable....................................................................................................... 939
25.3.6 Serial Clock Control ............................................................................................ 939
25.3.7 Using the SPI Mode With Low-Power Modes............................................................... 940
25.3.8 SPI Interrupts.................................................................................................... 940
25.4 eUSCI_A SPI Registers.................................................................................................. 942
25.4.1 UCAxCTLW0 Register ......................................................................................... 943
25.4.2 UCAxBRW Register ............................................................................................ 944
25.4.3 UCAxSTATW Register......................................................................................... 945
25.4.4 UCAxRXBUF Register ......................................................................................... 946
25.4.5 UCAxTXBUF Register ......................................................................................... 947
25.4.6 UCAxIE Register................................................................................................ 948
25.4.7 UCAxIFG Register.............................................................................................. 949
25.4.8 UCAxIV Register................................................................................................ 950
25.5 eUSCI_B SPI Registers.................................................................................................. 951
25.5.1 UCBxCTLW0 Register ......................................................................................... 952
25.5.2 UCBxBRW Register ............................................................................................ 953
25.5.3 UCBxSTATW Register......................................................................................... 953
25.5.4 UCBxRXBUF Register ......................................................................................... 954
25.5.5 UCBxTXBUF Register ......................................................................................... 954
25.5.6 UCBxIE Register ............................................................................................... 955
25.5.7 UCBxIFG Register.............................................................................................. 955
25.5.8 UCBxIV Register................................................................................................ 956
26 Enhanced Universal Serial Communication Interface (eUSCI) – I
2
C Mode ................................ 957
26.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview ................................... 958
26.2 eUSCI_B Introduction – I
2
C Mode...................................................................................... 958
26.3 eUSCI_B Operation – I
2
C Mode ........................................................................................ 959
26.3.1 eUSCI_B Initialization and Reset............................................................................. 960
26.3.2 I
2
C Serial Data .................................................................................................. 960
26.3.3 I
2
C Addressing Modes ......................................................................................... 961
26.3.4 I
2
C Module Operating Modes ................................................................................. 962
26.3.5 Glitch Filtering ................................................................................................... 972
26.3.6 I
2
C Clock Generation and Synchronization.................................................................. 972
26.3.7 Byte Counter .................................................................................................... 973
26.3.8 Multiple Slave Addresses...................................................................................... 974
26.3.9 Using the eUSCI_B Module in I
2
C Mode With Low-Power Modes....................................... 975
26.3.10 eUSCI_B Interrupts in I
2
C Mode ............................................................................ 975
26.4 eUSCI_B I2C Registers.................................................................................................. 977
26.4.1 UCBxCTLW0 Register ......................................................................................... 978
26.4.2 UCBxCTLW1 Register ......................................................................................... 980
26.4.3 UCBxBRW Register ............................................................................................ 982
26.4.4 UCBxSTATW.................................................................................................... 982
26.4.5 UCBxTBCNT Register ......................................................................................... 983
26.4.6 UCBxRXBUF Register ......................................................................................... 984
26.4.7 UCBxTXBUF .................................................................................................... 984
26.4.8 UCBxI2COA0 Register......................................................................................... 985
26.4.9 UCBxI2COA1 Register......................................................................................... 986
26.4.10 UCBxI2COA2 Register ....................................................................................... 986
26.4.11 UCBxI2COA3 Register ....................................................................................... 987
26.4.12 UCBxADDRX Register ....................................................................................... 987
26.4.13 UCBxADDMASK Register ................................................................................... 988