DDR4 LRDIMM MTA36ASF4G72LZ-32GB 数据手册

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"LRDDIM_Micro_asf36c4gx72lz 是Micro公司生产的一款DDR4 LRDIMM内存模块，其详细规格和功能在提供的datasheet中有详细描述。该内存模块支持DDR4标准功能，具有288引脚，采用命令/地址/控制寄存器和数据缓冲设计，适用于服务器和高性能计算平台。" LRDDIM_Micro_asf36c4gx72lz是DDR4类型的Load Reduced Dual In-Line Memory Module (LRDIMM)，它在内存技术中扮演着关键角色，主要设计用于提高数据中心和服务器的性能。这款内存模块的主要特点包括： 1. **功能特性**：按照DDR4组件数据表定义的功能和操作进行设计，提供高效能的内存解决方案。 2. **引脚数量**：拥有288个引脚，采用命令/地址/控制寄存器，以及数据缓冲设计，确保高速数据传输。 3. **传输速率**：支持PC4-2666和PC4-2400两种传输速率，分别对应3200 MT/s和2400 MT/s的数据传输速度。 4. **容量**：提供32GB的内存容量，由4GBx72的DRAM芯片组成，即72片4GB的DRAM芯片。 5. **电压**：工作电压VDD为1.20V（标称值），VPP为2.5V（标称值），VDDSPD也为2.5V（标称值）。 6. **错误检测与校正**：支持ECC（Error Correction Code）错误检测和校正技术，提高数据完整性。 7. **动态开/关阻抗匹配（ODT）**：对数据、时钟和掩码信号进行名义和动态的ODT，确保信号质量。 8. **低功耗自刷新（LPASR）**：在低功耗模式下，内存能够自动进入自刷新状态，减少能耗。 9. **内部VREFDQ生成**：内置可调节的VREFDQ生成电路，优化信号参考电压。 10. **双列设计**：采用双列配置，提升内存访问效率。 11. **I2C温度传感器**：板载I2C温度传感器，集成的SPD（Serial Presence Detect）EEPROM，用于监控和管理内存模块的温度和配置信息。 12. **内部银行结构**：16个内部银行，分为4组每组4个银行，优化多任务并发处理能力。 13. **固定突发切分（BC4）和突发长度（BL8）**：通过模块寄存器集（MRS）实现固定BC4和BL8，提供灵活的内存访问模式。 14. **可选BC4或BL8 OTF**：允许在运行过程中动态选择BC4或BL8模式。 15. **金边触点**：使用金质边缘触点，确保良好的电气接触和耐久性。 16. **无卤素设计**：符合环保要求，不含卤素元素。 17. **飞线拓扑**：优化信号路径，减少信号延迟。 18. **复用命令和地址总线**：提高系统资源利用率。 19. **控制、命令和地址总线终止**：改善信号完整性，降低噪声影响。 20. **模块尺寸**：高度为31.25mm（1.23英寸），符合标准LRDIMM的尺寸要求。此外，LRDDIM_Micro_asf36c4gx72lz还提供了不同工作温度范围的选项，例如商业级产品，其工作温度范围为0°C到95°C。这款内存模块的设计考虑了服务器环境的需求，如高密度、高可靠性及能效，是现代数据中心和高性能计算平台的理想选择。

Table 5: Pin Descriptions (Continued)

Symbol Type Description

ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the

DDR4 SDRAM. When enabled, ODT (R

) is applied only to each DQ, DQS_t, DQS_c, DM_n/

DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 configurations (when the TDQS function is ena-

bled via the mode register). For the x16 configuration, R

is applied to each DQ, DQSU_t,

DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode

registers are programmed to disable R

PARITY Input Parity for command and address: This function can be enabled or disabled via the mode

WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be maintained at the rising edge of the

clock and at the same time as command and address with CS_n LOW.

RAS_n/A16

CAS_n/A15

WE_n/A14

Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the com-

mand and/or address being entered and have multiple functions. For example, for activation

with ACT_n LOW, these are addresses like A16, A15, and A14, but for a non-activation com-

mand with ACT_n HIGH, these are command pins for READ, WRITE, and other commands de-

fined in Command Truth Table.

RESET_n CMOS Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW and inactive when RE-

SET_n is HIGH. RESET_n must be HIGH during normal operation.

SAx Input

Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range

on the I

C bus.

SCL Input

Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to

and from the temperature sensor/SPD EEPROM on the I

C bus.

DQx, CBx I/O Data input/output and check bit input/output: Bidirectional data bus. DQ represents

DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If cyclic re-

dundancy checksum (CRC) is enabled via the mode register, the CRC code is added at the end of

the data burst. Any one or all of DQ0, DQ1, DQ2, or DQ3 may be used for monitoring of inter-

nal V

REF

level during test via mode register setting MR[4] A[4] = HIGH; training times change

when enabled.

DM_n/DBI_n/

TDQS_t (DMU_n,

DBIU_n), (DML_n/

DBIl_n)

I/O Input data mask and data bus inversion: DM_n is an input mask signal for write data. Input

data is masked when DM_n is sampled LOW coincident with that input data during a write ac-

cess. DM_n is sampled on both edges of DQS. DM is multiplexed with the DBI function by the

mode register A10, A11, and A12 settings in MR5. For a x8 device, the function of DM or TDQS

is enabled by the mode register A11 setting in MR1. DBI_n is an input/output identifying

whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/

output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH. TDQS is only

supported in x8 SDRAM configurations (TDQS is not valid for UDIMMs).

SDA I/O Serial Data: Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM/TS

combo device.

DQS_t

DQS_c

DQSU_t

DQSU_c

DQSL_t

DQSL_c

I/O Data strobe: Output with read data, input with write data. Edge-aligned with read data, cen-

tered-aligned with write data. For x16 configurations, DQSL corresponds to the data on

DQ[7:0], and DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS

corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differen-

tial data strobe only and does not support a single-ended data strobe.

ALERT_n Output Alert output: Possesses functions such as CRC error flag and command and address parity error

flag as output signal. If a CRC error occurs, ALERT_n goes LOW for the period time interval and

returns HIGH. If an error occurs during a command address parity check, ALERT_n goes LOW un-

til the on-going DRAM internal recovery transaction is complete. During connectivity test mode,

this pin functions as an input. Use of this signal is system-dependent. If not connected as signal,

ALERT_n pin must be connected to V

on DIMMs.

EVENT_n Output Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical tem-

perature thresholds have been exceeded. This pin has no function (NF) on modules without

temperature sensors.

32GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM

Pin Descriptions

09005aef863a8960

asf36c4gx72lz.pdf - Rev. D 8/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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