Skylake平台Intel Open Source HD图形程序员参考手册

GPU

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Doc Ref # IHD-OS-SKL-Vol 5-05.16

MI Client

Access Modes

Display/Overlay

Engines (internal)

Read of display, overlay, cursor and VGA data.

Media Engines

Read and write of media content and media processing.

uController

Read/Write (DMA) functions for u-controller and scheduler.

Graphics Memory Addressing Overview

The Memory Interface function provides access to graphics memory (GM) clients. It accepts memory

addresses of various types, performs a number of optional operations along address paths, and

eventually performs reads and writes of graphics memory data using the resultant addresses. The

remainder of this subsection will provide an overview of the graphics memory clients and address

operations.

Graphics Address Path

Graphics Address Path shows the internal graphics memory address path, connection points, and optional

operations performed on addresses. Externally-supplied addresses are normalized to zero-based

Graphics Memory (GM) addresses (GM_Address). If the GM address is determined to be a tiled address

(based on inclusion in a fenced region or via explicit surface parameters), address tiling is performed. At

this point the address is considered a Logical Memory address, and is translated into a Physical Memory

address via the GTT and associated TLBs. The physical memory location is then accessed.

CPU accesses to graphics memory are sent back on the ring to snoop. Hence pages that are mapped

cacheable in the GTT will be coherent with the CPU cache if accessed through graphics memory aperture.

Doc Ref # IHD-OS-SKL-Vol 5-05.16

Graphics Memory Address Spaces

The Graphics Memory Address Spaces table lists the five supported Graphics Memory Address Spaces.

Note that the Graphics Memory Range Removal function is automatically performed to transform system

addresses to internal, zero-based Graphics Addresses.

Graphics Memory Address Types

Address

Type

Description

Range

Gen9 (BXT)

GMADR

Address range allocated via the Device 2 (integrated graphics

device) GMADR register. The processor and other peer (DMI)

devices utilize this address space to read/write graphics data

that resides in Main Memory. This address is internally

converted to a GM_Address.

This is a 4 GB BAR

above physical

memory.

128 MB, 256

MB, 512 MB,

1GB, 2GB, 4GB

GTTMMADR

The combined Graphics Translation Table Modification Range

and Memory Mapped Range. The range requires 16 MB

combined for MMIO and Global GTT aperture, with 8MB of that

used by MMIO and 8MB used by GTT. GTTADR will begin at

GTTMMADR 8MB while the MMIO base address will be the

same as GTTMMADR.

For the Global GTT, this range is defined as a memory BAR in

graphics device config space. It is an alias into which software is

required to write Page Table Entry values PTEs. Software may

read PTE values from the global Graphics Translation Table GTT.

PTEs cannot be written directly into the global GTT memory

area.

This is a 16MB BAR

above physical

memory.

16 MB

(2 MB MMIO +

6 MB reserved

+ 8 MB GGTT)

GSM

GTT Stolen Memory. It is an 8 MB (max) region taken out of

physical memory to store the Global GTT entries for page

translations specific to GFX driver use.

It is accessible via GTTMMADR from the CPU path however

GPU/DE can access the same region directly.

This is an 8 MB

region in physical

memory not visible

to OS.

1 MB, 2 MB, 4

MB, 8 MB

DSM

Data stolen memory, the size is determined with GMS filed (8

bits) with MAX size of 4 GB.

This is a stolen memory which can be accessed via GMADR for

CPU and directly for GPU/DE.

Size is programmable with 32 MB multiplier.

First 4KB of DSM has to be reserved for GFX hardware use.

This is a max of 4

GB stolen physical

memory for GFX

data structures.

0 MB, 32 MB,

64 MB, 96 MB,

...4096MB

Next level breakdown for GTTMMADR is given below.

Software is allowed to use range x17_0000 to x17_FFFF as the Null range.

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