"TI DS99R101/DS99R102 FPD-Link解串器产品手册"
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The DS99R101/DS99R102 is a high-performance FPD-Link deserializer designed for 24-bit LVDS data transmission at speeds ranging from 3MHz to 40MHz. Featuring a 48-pin TQFP package and a pure CMOS .35 μm process, this serializer and deserializer pair offers users the flexibility to select the clock edge for parallel data transmission. With a power supply range of 3.3V ± 10% on both the transmitter and receiver, as well as an operating temperature range of 0°C to 70°C, the DS99R101/DS99R102 ensures reliable signal integrity in a variety of environmental conditions. Additionally, the internal DC balancing encode/decode functionality further enhances the performance and robustness of this LVDS serializer and deserializer. Whether used in automotive, industrial, or other applications requiring high-speed data transmission, the DS99R101/DS99R102 offers a versatile and efficient solution for demanding communication requirements.
80%
20%
80%
20%
Vdiff = 0V
t
LLHT
t
LHLT
Differential
Signal
Vdiff = (DOUT+) - (DOUT-)
100:
DOUT+
DOUT-
10 pF
10 pF
RCLK
ODD ROUT
EVEN ROUT
Signal PatternDevice Pin Name
TCLK
ODD DIN
EVEN DIN
Signal PatternDevice Pin Name
DS99R101, DS99R102
SNLS240D –MARCH 2007–REVISED APRIL 2013
www.ti.com
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
DRDL
Deserializer PLL Lock Time (Figure 14)
(3)
3 MHz 5 50 ms
from Powerdown
(4) (5) (1)
40 MHz 5 50 ms
RxIN_TOL_L Receiver INput TOLerance (Figure 16) 3 MHz–40 MHz
0.25 UI
Left
(6) (1) (7)
RxIN_TOL_R Receiver INput TOLerance (Figure 16) 3 MHz–40 MHz
0.25 UI
Right
(6) (1) (7)
(4) t
DRDL
is the time required by the deserializer to obtain lock when exiting powerdown mode. t
DRDL
is specified with an external
synchronization pattern.
(5) The Deserializer PLL lock time (t
DRDL
) may vary depending on input data patterns and the number of transitions within the pattern.
(6) RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.
(7) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
AC Timing Diagrams and Test Circuits
Figure 1. Serializer Input Checker-board Pattern
Figure 2. Deserializer Output Checker-board Pattern
Figure 3. Serializer LVDS Output Load and Transition Times
6 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS99R101 DS99R102
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