FLASH MEMORY
9
Preliminary
K9GAG08U0M
K9GAG08B0M
K9LBG08U1M
Product Introduction
The K9GAG08X0M is a 16,896Mbit(17,716,740,096 bit) memory organized as 524,288 rows(pages) by 4,224x8 columns. Spare 128
columns are located from column address of 4,096~4,223. A 4,224-byte data register is connected to memory cell arrays for accom-
modating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array
is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block
consists of two NAND structured strings. A NAND structure consists of 32 cells. A cell has 2-bit data. Total 2,162,688 NAND cells
reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block
basis. The memory array consists of 4,096 separately erasable 512K-byte blocks. It indicates that the bit by bit erase operation is pro-
hibited on the K9GAG08X0M.
The K9GAG08X0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE
to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 2112M-byte physical space
requires 32 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-
ation, however, only three row address cycles are used. Device operations are selected by writing specific commands into the com-
mand register. Table 1 defines the specific commands of the K9GAG08X0M.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
NOTE : 1. Random Data Input/Output can be executed in a page.
2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh.
3. Two-Plane Random Data out must be used after Two-Plane Read operation
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
Function 1st Set 2nd Set Acceptable Command during Busy
Read 00h 30h
Read for Copy Back 00h 35h
Read ID 90h -
Reset FFh - O
Page Program 80h 10h
Copy-Back Program 85h 10h
Block Erase 60h D0h
Random Data Input
(1)
85h -
Random Data Output
(1)
05h E0h
Read Status 70h O
Read Status 2 F1h O
Two-Plane Read
(3)
60h----60h 30h
Two-Plane Read for Copy-Back 60h----60h 35h
Two-Plane Random Data Output
(1) (3)
00h----05h E0h
Two-Plane Page Program
(2)
80h----11h 81h----10h
Two-Plane Copy-Back Program
(2)
85h----11h 81h----10h
Two-Plane Block Erase 60h----60h D0h
Page Program with 2KB Data
(2)
80h----11h 80h----10h
Copy-Back Program with 2KB Data
(2)
85h----11h 85h----10h
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