三星2GB NAND闪存芯片K9GAG08U0M技术规格

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"三星K9GAG08U0M是一款2GB NAND闪存芯片的数据手册，这份资料在业界较为罕见。文档可能包含了该芯片的技术规格、功能描述、操作指南以及修订历史等关键信息。" 三星的K9GAG08U0M是一款2GB的NAND闪存芯片，主要用于数据存储。NAND闪存是一种非易失性存储技术，即使在断电后也能保持数据。这种类型的存储器广泛应用于移动设备、固态硬盘（SSD）、数字相机、USB驱动器等产品中，因其高密度、快速读写速度和低功耗特性而受到青睐。此 datasheet 提供了关于K9GAG08U0M的初步信息，暗示其中可能包含以下内容： 1. 产品规格：包括芯片的存储容量（2GB），位宽（2Gx8位），电压要求，I/O接口标准，最大读写速度，以及工作温度范围等。 2. 电气特性：详述了芯片的电源电压(Vcc)、输入/输出电压(Vio)，以及各种操作模式下的电流消耗。 3. 编程和擦除机制：NAND闪存芯片通过编程和擦除操作来存储和清除数据， datasheet 可能会详细解释这些过程，包括编程脉冲、擦除时间以及相关的耐久性指标。 4. 错误检测与纠正：可能包含了内置的错误校正代码(ECC)机制，确保数据的可靠性。 5. 地址映射：说明如何将逻辑地址转换为物理地址，以便高效访问存储单元。 6. 命令和时序：定义了芯片与控制器之间的通信协议，包括各种命令的时序图和参数。 7. 可靠性与耐用性：包括擦写周期(P/E cycles)限制，数据保留时间，以及可能的故障模式和应对策略。 8. 封装和引脚定义：描述了芯片的物理封装形式和每个引脚的功能。 9. 安全与兼容性：可能会指出该芯片不适用于生命维持设备、关键医疗设备、军事或防御应用，因为这些领域对产品的可靠性和安全性有特殊要求。 10. 修订历史：记录了 datasheet 的更新情况，对于跟踪芯片的改进和修正非常重要。请注意，由于原始信息没有提供完整的 datasheet 内容，以上分析基于一般NAND闪存芯片 datasheet 的常见部分进行推测。实际 datasheet 将包含更详细的技术信息和具体规格。对于具体的应用设计和集成，应参考完整文档以获取准确信息。

FLASH MEMORY

Preliminary

K9GAG08U0M

K9GAG08B0M

K9LBG08U1M

Product Introduction

The K9GAG08X0M is a 16,896Mbit(17,716,740,096 bit) memory organized as 524,288 rows(pages) by 4,224x8 columns. Spare 128

columns are located from column address of 4,096~4,223. A 4,224-byte data register is connected to memory cell arrays for accom-

modating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array

is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block

consists of two NAND structured strings. A NAND structure consists of 32 cells. A cell has 2-bit data. Total 2,162,688 NAND cells

reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block

basis. The memory array consists of 4,096 separately erasable 512K-byte blocks. It indicates that the bit by bit erase operation is pro-

hibited on the K9GAG08X0M.

The K9GAG08X0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades

to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by

bringing WE

to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For

example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block

erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 2112M-byte physical space

requires 32 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that

order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-

ation, however, only three row address cycles are used. Device operations are selected by writing specific commands into the com-

mand register. Table 1 defines the specific commands of the K9GAG08X0M.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another

page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and

data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh.

3. Two-Plane Random Data out must be used after Two-Plane Read operation

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

Function 1st Set 2nd Set Acceptable Command during Busy

Read 00h 30h

Read for Copy Back 00h 35h

Read ID 90h -

Reset FFh - O

Page Program 80h 10h

Copy-Back Program 85h 10h

Block Erase 60h D0h

Random Data Input

(1)

85h -

Random Data Output

(1)

05h E0h

Read Status 70h O

Read Status 2 F1h O

Two-Plane Read

(3)

60h----60h 30h

Two-Plane Read for Copy-Back 60h----60h 35h

Two-Plane Random Data Output

(1) (3)

00h----05h E0h

Two-Plane Page Program

(2)

80h----11h 81h----10h

Two-Plane Copy-Back Program

(2)

85h----11h 81h----10h

Two-Plane Block Erase 60h----60h D0h

Page Program with 2KB Data

(2)

80h----11h 80h----10h

Copy-Back Program with 2KB Data

(2)

85h----11h 85h----10h

FLASH MEMORY

Preliminary

K9GAG08U0M

K9GAG08B0M

K9LBG08U1M

ABSOLUTE MAXIMUM RATINGS

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.

Maximum DC voltage on input/output pins is V

CC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter Symbol

Rating

Unit

2.7V / 3.3V Device

Voltage on any pin relative to V

VCC -0.6 to + 4.6

IN -0.6 to + 4.6

I/O -0.6 to Vcc+0.3 (<4.6V)

Temperature Under Bias

K9XXG08X0M-XCB0

BIAS

-10 to +125

°C

K9XXG08X0M-XIB0 -40 to +125

Storage Temperature

K9XXG08X0M-XCB0

STG -65 to +150 °C

K9XXG08X0M-XIB0

Short Circuit Current Ios 5 mA

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9XXG08X0M-XCB0 :TA=0 to 70°C, K9GAG08X0M-XIB0:TA=-40 to 85°C)

Parameter Symbol

K9GAG08B0M(2.7V) K9XXG08UXM(3.3V)

Unit

Min Typ. Max Min Typ. Max

Supply Voltage V

CC 2.5 2.7 2.9 2.7 3.3 3.6 V

Supply Voltage V

SS 000000V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

2. Typical value is measured at Vcc=3.3V, T

A=25°C. Not 100% tested.

3. The typical value of the K9LBG08U1M’s

ISB2 is 20µA and the maximum value is 100µA.

Parameter Symbol Test Conditions

K9GAG08X0M

Unit2.7V 3.3V

Min Typ Max Min Typ Max

Operating

Current

Page Read with

Serial Access

CC1

tRC=25ns

=VIL, IOUT=0mA

- 15 30 - 15 30

Program I

CC2-

Erase I

CC3-

Stand-by Current(TTL) I

SB1CE=VIH, WP=0V/VCC --1 --1

Stand-by Current(CMOS) I

SB2CE=VCC-0.2, WP=0V/VCC - 10 50 - 10 50

µA

Input Leakage Current I

LI VIN=0 to Vcc(max) - - ±10 - - ±10

Output Leakage Current I

LO VOUT=0 to Vcc(max) - - ±10 - - ±10

Input High Voltage

(1)

0.8

xVcc

Vcc

+0.3

0.8

xVcc

Vcc

+0.3

Input Low Voltage, All inputs

(1)

--0.3-

0.2

xVcc

-0.3 -

0.2

xVcc

Output High Voltage Level V

K9GAG08B0M :IOH=-100µA

K9GAG08U0M :I

OH=-400µA

-0.4

--2.4--

Output Low Voltage Level V

K9GAG08B0M :IOL=100uA

K9GAG08U0M :I

OL=2.1mA

--0.4--0.4

Output Low Current(R/B

)IOL(R/B)

K9GAG08B0M :V

OL=0.1V

K9GAG08U0M :V

OL=0.4V

34- 810-mA

FLASH MEMORY

Preliminary

K9GAG08U0M

K9GAG08B0M

K9LBG08U1M

CAPACITANCE(TA=25°C, VCC=2.7V/3.3V, f=1.0MHz)

NOTE :1. Capacitance is periodically sampled and not 100% tested.

CI/O(W)* and CIN(W)* are tested at wafer level.

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance

I/O VIL=0V - 5 pF

I/O(W)* VIL=0V - 5 pF

Input Capacitance

IN VIN=0V - 5 pF

IN(W)* VIN=0V - 5 pF

VALID BLOCK

NOTE :

1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is

presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits which cause status fail-

ure during program and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate

management of initial invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.

3. The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations.

* : Each K9GAG08U0M chip in the K9LBG08U1M has Maximum 100 invalid blocks

Parameter Symbol Min Typ. Max Unit

K9GAG08X0M N

VB 3,996 - 4,096 Blocks

K9LBG08U1M

7,992 - 8,192 Blocks

MODE SELECTION

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

CLE ALE CE WE RE WP Mode

HLL HX

Read Mode

Command Input

L H L H X Address Input(5clock)

HLL HH

Write Mode

Command Input

L H L H H Address Input(5clock)

L L L H H Data Input

L L L H X Data Output

XXXXHX During Read(Busy)

XXXXXH During Program(Busy)

XXXXXH During Erase(Busy)

(1)

X X X L Write Protect

XXHXX

0V/V

(2)

Stand-by

AC TEST CONDITION

(K9XXG08X0M-XCB0: TA=0 to 70°C, K9XXG08X0M-XIB0:TA=-40 to 85°C,

K9GAG08B0M: Vcc=2.5V~2.9V, K9XXG08UXM: Vcc=2.7V~3.6V unless otherwise noted)

Parameter K9GAG08B0M K9XXG08UXM

Input Pulse Levels 0V to Vcc 0V to Vcc

Input Rise and Fall Times 5ns 5ns

Input and Output Timing Levels Vcc/2 Vcc/2

Output Load 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF

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