
GL3232S Design Guide
© 2018 Genesys Logic, Inc. - All rights reserved. Page 4
GLI Confidential
Table of Contents
CHAPTER 1 INTRODUCTION .......................................................................................... 7
1.1 GL3232S Chip Overview .......................................................................................... 7
CHAPTER 2 CIRCUIT DESIGN GUIDELINES ............................................................... 8
2.1 AC Coupling Capacitance ........................................................................................ 8
2.2 Power .......................................................................................................................... 8
2.2.1 Note for the Internal Switching Regulator ...................................................... 8
2.2.2 Capacitance of Power ........................................................................................ 8
2.3 PMOS Capacitor ....................................................................................................... 9
2.4 Components of Internal Switching Regulator ........................................................ 9
CHAPTER 3 PCB LAYOUT GUIDELINES ..................................................................... 10
3.1 PCB Layer ............................................................................................................... 10
3.2 Recommended Layout Sequence ........................................................................... 10
3.3 USB Differential Pair .............................................................................................. 10
3.3.1 Maximum Length of USB Differential Trace ................................................ 10
3.3.2 Mismatch of USB Differential Trace Length ................................................. 11
3.3.3 USB Differential Pair Impedance ................................................................... 11
3.4 Adjacent Space Gap ................................................................................................ 11
3.5 Trace Bend ............................................................................................................... 11
3.6 Reference Plane ....................................................................................................... 12
3.7 Differential Pair Layout ......................................................................................... 13
3.8 Prevent Stubs on Differential Traces ..................................................................... 14
3.9 AC Coupling Capacitor Placement ....................................................................... 14
3.10 Crystal Wiring ......................................................................................................... 14
3.11 Card Interface ......................................................................................................... 15
3.11.1 Mismatch of Card Interface Trace Length .................................................. 15
3.11.2 Card Interface Trace Impedance .................................................................. 16
3.11.3 Maximum Length of Card Interface Trace ................................................. 16
3.11.4 SD UHS-II Interface Layout ......................................................................... 16
3.12 Internal Switching Regulator Layout Guideline .................................................. 16
3.13 GL3232S Footprint ................................................................................................. 17