功率MOSFET设计指南：高速门驱动电路解析

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"功率MOSFET设计与应用指南" 在电力电子领域，功率MOSFET（金属氧化物半导体场效应晶体管）是不可或缺的关键元件，尤其在高速开关应用中。本文档，"DesignAndApplicationGuideforHighSpeed MOSFETGateDriveCircuits"由Laszlo Balogh撰写，旨在为设计者提供一个系统性的方法来构建高性能的MOSFET门驱动电路。它涵盖了从基础到高级的各种主题，对各种设计挑战提供了全面的解决方案，无论工程师的经验水平如何，都能从中受益。 MOSFET技术的核心在于其能够通过控制栅极电压来开关主电流通路，因此在高效率、高速度的电源转换系统中广泛应用。文档首先介绍了MOSFET的基本工作原理和技术，以及其开关操作的过程。在讨论中，作者深入探讨了寄生组件（如电感、电容）对电路性能的影响，以及在瞬态和极端工作条件下的行为。设计高侧和地参考门驱动电路是MOSFET驱动电路设计中的关键部分。文档详细阐述了这两种电路的设计过程，包括如何处理共模噪声和隔离问题。AC耦合和变压器隔离方案也被详细解析，这些方案在确保电路安全和提高效率方面起着重要作用。同步整流器应用中的MOSFET门驱动需求是另一个专门章节的主题。同步整流技术利用MOSFET替代二极管以降低损耗，提升效率，因此对门驱动电路的要求更为严格。文档深入分析了这些特殊需求，以确保MOSFET在同步整流器中的可靠工作。为了使理论知识更具实践性，文档还提供了多个逐步的数值设计示例，帮助读者将理论知识应用于实际设计过程中。这些示例通过具体的计算和分析，让读者更直观地理解如何解决设计中遇到的具体问题。这份设计和应用指南是电力电子工程师的宝贵资源，无论是新手还是经验丰富的专家，都能从中获得对功率MOSFET驱动电路设计的深刻理解和实用技巧。通过学习和实践，工程师们将能更好地应对高速开关应用中的挑战，优化系统的性能和可靠性。

2-7

This is accomplished by charging the C

and

capacitors, thus gate current is now split

between the two components. While these

capacitors are being charged, the drain current is

still constant, and the drain-to-source voltage is

slightly decreasing as the on-resistance of the

device is being reduced.

B. Turn-Off Procedure

The description of the turn-off procedure for

the MOSFET transistor is basically back tracking

the turn-on steps from the previous section. Start

with V

being equal to V

DRV

and the current in

the device is the full load current represented by

in Fig. 3. The drain-to-source voltage is

being defined by I

and the R

DS(on)

of the

MOSFET. The four turn-off steps are shown in

Fig. 5. for completeness.

DRV

GATE

G,I

3 421

Fig. 5. MOSFET turn-off time intervals

The first time interval is the turn-off delay

which is required to discharge the C

ISS

capacitance from its initial value to the Miller

plateau level. During this time the gate current is

supplied by the C

ISS

capacitor itself and it is

flowing through the C

and C

capacitors of

the MOSFET. The drain voltage of the device is

slightly increasing as the overdrive voltage is

diminishing. The current in the drain is

unchanged.

In the second period, the drain-to-source

voltage of the MOSFET rises from I

⋅R

DS(on)

the final V

DS(off)

level, where it is clamped to the

output voltage by the rectifier diode according to

the simplified schematic of Fig. 3. During this

time period – which corresponds to the Miller

plateau in the gate voltage waveform - the gate

current is strictly the charging current of the C

capacitor because the gate-to-source voltage is

constant. This current is provided by the bypass

capacitor of the power stage and it is subtracted

from the drain current. The total drain current

still equals the load current, i.e. the inductor

current represented by the DC current source in

Fig. 3.

The beginning of the third time interval is

signified by the turn-on of the diode, thus

providing an alternative route to the load current.

The gate voltage resumes falling from V

GS,Miller

to V

. The majority of the gate current is

coming out of the C

capacitor, because the C

capacitor is virtually fully charged from the

previous time interval. The MOSFET is in linear

operation and the declining gate-to-source

voltage causes the drain current to decrease and

reach near zero by the end of this interval.

Meanwhile the drain voltage is steady at V

DS(off)

due to the forward biased rectifier diode.

The last step of the turn-off procedure is to

fully discharge the input capacitors of the device.

is further reduced until it reaches 0V. The

bigger portion of the gate current, similarly to the

third turn-off time interval, supplied by the C

capacitor. The drain current and the drain voltage

in the device are unchanged.

2-8

Summarizing the results, it can be concluded

that the MOSFET transistor can be switched

between its highest and lowest impedance states

(either turn-on or turn-off) in four time intervals.

The lengths of all four time intervals are a

function of the parasitic capacitance values, the

required voltage change across them and the

available gate drive current. This emphasizes the

importance of the proper component selection

and optimum gate drive design for high speed,

high frequency switching applications.

Characteristic numbers for turn-on, turn-off

delays, rise and fall times of the MOSFET

switching waveforms are listed in the transistor

data sheets. Unfortunately, these numbers

correspond to the specific test conditions and to

resistive load, making the comparison of

different manufacturers’ products difficult. Also,

switching performance in practical applications

with clamped inductive load is significantly

different from the numbers given in the data

sheets.

C. Power Losses

The switching action in the MOSFET

transistor in power applications will result in

some unavoidable losses, which can be divided

into two categories.

The simpler of the two loss mechanisms is

the gate drive loss of the device. As described

before, turning-on or off the MOSFET involves

charging or discharging the C

ISS

capacitor. When

the voltage across a capacitor is changing, a

certain amount of charge has to be transferred.

The amount of charge required to change the

gate voltage between 0V and the actual gate

drive voltage V

DRV

, is characterized by the

typical gate charge vs. gate-to-source voltage

curve in the MOSFET datasheet. An example is

shown in Fig. 6.

This graph gives a relatively accurate worst

case estimate of the gate charge as a function of

the gate drive voltage. The parameter used to

generate the individual curves is the drain-to-

source off state voltage of the device. V

DS(off)

influences the Miller charge – the area below the

flat portion of the curves – thus also, the total

gate charge required in a switching cycle. Once

the total gate charge is obtained from Fig. 6, the

gate charge losses can be calculated as:

DRVGDRVGATE

fQVP ⋅⋅=

where V

DRV

is the amplitude of the gate drive

waveform and f

DRV

is the gate drive frequency –

which is in most cases equal to the switching

frequency. It is interesting to notice that the

⋅f

DRV

term in the previous equation gives the

average bias current required to drive the gate.

The power lost to drive the gate of the

MOSFET transistor is dissipated in the gate

drive circuitry. Referring back to Figures 4 and

5, the dissipating components can be identified

as the combination of the series ohmic

impedances in the gate drive path. In every

switching cycle the required gate charge has to

pass through the driver output impedances, the

external gate resistor, and the internal gate mesh

resistance. As it turns out, the power dissipation

is independent of how quickly the charge is

delivered through the resistors. Using the resistor

designators from Figures 4 and 5, the driver

power dissipation can be expressed as:

OFFDRV,ONDRV,DRV

IG,GATELO

DRVGDRVLO

OFFDRV,

IG,GATEHI

DRVGDRVHI

ONDRV,

PPP

RRR

fQVR

RRR

fQVR

⋅⋅⋅

⋅=

⋅⋅⋅

⋅=

Vgs, Gate-to-Source Voltage (V)

Qg, Total Gate Charge (nC)

DRV

Fig. 6. Typical gate charge vs. gate-to-source

voltage.

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