ARM指令集详解：数据处理与程序控制

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"ARM指令集概要手册" ARM指令集是微处理器架构中广泛使用的指令集，尤其在嵌入式系统和移动设备中占据主导地位。本手册提供了对ARM指令集的详细概述，涵盖多种指令类别，帮助理解其工作原理。 1. 数据处理类指令：这些指令主要用于CPU内部的数据计算，不涉及内存操作。它们包括算术运算（如加、减、乘、除）、逻辑运算（如与、或、异或、非）以及位操作（如位移、位带通配符）。这类指令使得CPU能够执行基本的算术和逻辑运算，是程序执行的核心部分。 2. Load/Store指令： Load指令用于将内存中的数据加载到CPU寄存器，而Store指令则将寄存器中的数据存储回内存。这些指令是ARM指令集中的关键部分，因为大多数数据处理都需要先将数据加载到寄存器，处理后再写回内存。它们是CPU与外部世界交互的主要桥梁。 3. 跳转指令：跳转指令，也称为分支指令，用于改变程序的执行流程。它们包括无条件跳转、条件跳转、子程序调用和返回等，使得程序可以根据条件执行不同的代码路径或执行函数调用。 4. 程序状态寄存器处理指令：程序状态寄存器（CPSR，Current Program Status Register）保存了程序运行时的关键状态信息，如标志位、中断禁止位等。通过这类指令，可以修改CPSR的内容，从而影响程序的控制流和异常处理。 5. 协处理器指令：协处理器是扩展CPU功能的硬件单元，如浮点运算、加密解密、数字信号处理等。协处理器指令允许CPU与协处理器交互，发送命令、读取或写入协处理器寄存器，增强CPU的处理能力。 6. 异常产生指令：异常产生指令用于触发异常事件，如中断、故障或陷阱。当程序需要处理中断请求、执行系统服务或者处理错误时，这些指令会被执行，将控制权转移给相应的异常处理程序。这个文档可能还包括了关于ARM架构的版本信息、修订历史、版权声明以及使用许可条款等内容。ARM架构的不断发展和完善确保了它能适应不断变化的计算需求，保持在嵌入式和移动计算领域的领先地位。对于开发者而言，深入理解和熟练运用ARM指令集是设计高效、优化代码的关键。

Preface

• The restriction that multiplication destination registers should be different from their source registers

is removed in ARMv6.

• In ARMv5, the

LDM

(2) and

STM

(2) ARM instructions have restrictions on the use of banked registers

by the immediately following instruction. These restrictions are removed from ARMv6.

• The rules determining which PSR bits are updated by an

MSR

instruction are clarified and extended to

cover the new PSR bits defined in ARMv6.

• In ARMv5, the Thumb

MOV

instruction behavior varies according to the registers used (see note). Two

changes are made in ARMv6.

— The restriction about the use of low register numbers in the

MOV

(3) instruction encoding is

removed.

— In order to make the new side-effect-free

MOV

instructions available to the assembler language

programmer without changing the meaning of existing assembler sources, a new assembler

syntax

CPY Rd,Rn

is introduced. This always assembles to the

MOV

(3) instruction regardless of

whether Rd and Rn are high or low registers.

Note

In ARMv5, the Thumb

MOV Rd,Rn

instructions have the following properties:

• If both Rd and Rn are low registers, the instruction is the

MOV

(2) instruction. This instruction sets the

N and Z flags according to the value transferred, and sets the C and V flags to 0.

• If either Rd or Rn is a high register, the instruction is the

MOV

(3) instruction. This instruction leaves

the condition flags unchanged.

This situation results in behavior that varies according to the registers used. The

MOV

(2) side-effects also limit

compiler flexibility on use of pseudo-registers in a global register allocator.

Naming of ARM/Thumb architecture versions

To name a precise version and variant of the ARM/Thumb architecture, the following strings are

concatenated:

1. The string

ARMv

2. The version number of the ARM instruction set.

3. Variant letters of the included variants.

4. In addition, the letter P is used after x to denote the exclusion of several instructions in the

ARMv5TExP variant.

The table Architecture versions on page xvii lists the standard names of the current (not obsolete)

ARM/Thumb architecture versions described in this manual. These names provide a shorthand way of

describing the precise instruction set implemented by an ARM processor. However, this manual normally

uses descriptive phrases such as T variants of architecture version 4 and above to avoid the use of lists of

architecture names.

Preface

Part B - Memory and System Architectures

Part B describes standard memory system features that are normally implemented by the System Control

coprocessor (coprocessor 15) in an ARM-based system. It contains the following chapters:

Chapter B1 Gives a brief overview of this part of the manual.

Chapter B2 The memory order model.

Chapter B3 Gives a general description of the System Control coprocessor and its use.

Chapter B4 Describes the standard ARM memory and system architecture based on the use of a Virtual

Memory System Architecture (VMSA) based on a Memory Management Unit (MMU).

Chapter B5 Gives a description of the simpler Protected Memory System Architecture (PMSA) based on

a Memory Protection Unit (MPU).

Chapter B6 Gives a description of the standard ways to control caches and write buffers in ARM

memory systems. This chapter is relevant both to systems based on an MMU and to systems

based on an MPU.

Chapter B7 Describes the Tightly Coupled Memory (TCM) architecture option for level 1 memory.

Chapter B8 Describes the Fast Context Switch Extension and Context ID support (ARMv6 only).

Part C - Vector Floating-point Architecture

Part C describes the Vector Floating-point (VFP) architecture. This is a coprocessor extension to the ARM

architecture designed for high floating-point performance on typical graphics and DSP algorithms.

Chapter C1 Gives a brief overview of the VFP architecture and information about its compliance with

the IEEE 754-1985 floating-point arithmetic standard.

Chapter C2 Describes the floating-point formats supported by the VFP instruction set, the floating-point

general-purpose registers that hold those values, and the VFP system registers.

Chapter C3 Describes the VFP coprocessor instruction set, organized by type of instruction.

Chapter C4 Contains detailed reference material on the VFP coprocessor instruction set, organized

alphabetically by instruction mnemonic.

Chapter C5 Contains detailed reference material on the addressing modes used by VFP instructions.

One of these is a traditional addressing mode, generating addresses for load/store

instructions. The remainder specify how the floating-point general-purpose registers and

instructions can be used to hold and perform calculations on vectors of floating-point values.

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