"TI-TL16C450.pdf：UART收发器详解及功能特点分析"
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更新于2024-03-16
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收藏 1.03MB PDF 举报 The TI-TL16C450 UART transceiver is a versatile communication device designed for serial data transmission and reception. It features a programmable Baud Rate Generator that can divide any input reference clock by 1 to 65535, allowing for flexible communication speed settings. The device also incorporates a full double buffering mechanism to ensure smooth data transfer without the need for precise synchronization.
In addition to basic data transmission, the UART supports standard asynchronous communication bits such as start, stop, and parity bits, which can be added or removed from the serial data stream as needed. The transceiver includes an independent receiver clock input, enabling seamless integration with various clock sources for optimal performance.
Overall, the TI-TL16C450 UART offers a reliable and efficient solution for serial communication in a wide range of applications. Its programmable features and robust design make it a versatile choice for data transmission needs. With its high level of flexibility and performance, the UART is a valuable tool for ensuring smooth and reliable communication between devices.
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
OH
‡
HIgh-level output voltage I
OH
= −1 mA 2.4 V
V
OL
‡
Low-level output voltage I
OL
= 1.6 mA 0.4 V
I
Ikg
Input leakage current
V
CC
= 5.25 V, V
SS
= 0,
±10
A
I
Ikg
Input leakage current
V
CC
= 5.25 V, V
SS
= 0,
V
I
= 0 to 5.25 V, All other terminals floating
±1
0
µA
I
OZ
High-impedance output current
V
CC
= 5.25 V, V
SS
= 0,
V
O
= 0 V to 5.25 V,
±20
A
I
OZ
High-impedance output current
V
O
= 0 V to 5.25 V,
Chip selected, write mode,or chip deselected
±2
0
µA
V
CC
= 5.25 V, T
A
= 25
°
C,
I
CC
Supply current
V
CC
= 5.25 V, T
A
= 25 C,
SIN, DSR, DCD, CTS, and RI at 2 V,
10
mA
I
CC
Supply current
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, Baud rate = 50 kbits/s,
10 mA
CC
All other inputs at 0.8 V, Baud rate = 50 kbits/s,
XTAL1 at 4 MHz, No load on outputs
C
XTAL1
Clock input capacitance
V = 0, V = 0,
15 20 pF
C
XTAL2
Clock output capacitance
V
CC
= 0, V
SS
= 0,
f = 1 MHz, T
A
= 25°C,
20 30 pF
C
i
Input capacitance
CC SS
f = 1 MHz, T
A
= 25
°
C,
All other terminals grounded
6 10 pF
C
o
Output capacitance
All other terminals grounded
10 20 pF
†
All typical values are at V
CC
= 5 V, T
A
= 25°C.
‡
These parameters apply for all outputs except XTAL2.
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER FIGURE MIN MAX UNIT
t
cR
Cycle time, read (t
w7
+ t
d8
+ t
d9
) 175 ns
t
cW
Cycle time, write (t
w6
+ t
d5
+ t
d6
) 175 ns
t
w5
Pulse duration, ADS low 2,3 15 ns
t
w6
Pulse duration, write strobe 2 80 ns
t
w7
Pulse duration, read strobe 3 80 ns
t
wMR
Pulse duration, master reset 1000 ns
t
su1
Setup time, address valid before ADS↑ 2,3 15 ns
t
su2
Setup time, CS valid before ADS↑ 2,3 15 ns
t
su3
Setup time, data valid before WR1↓ or WR2↑ 2 15 ns
t
h1
Hold time, address low after ADS↑ 2,3 0 ns
t
h2
Hold time, CS valid after ADS↑ 2,3 0 ns
t
h3
Hold time, CS valid after WR1↑ or WR2↓ 2 20 ns
t
h4
§
Hold time, address valid after WR1↑ or WR2↓ 2 20 ns
t
h5
Hold time, data valid after WR1↑ or WR2↓ 2 15 ns
t
h6
Hold time, CS valid after RD1↑ or RD2↓ 3 20 ns
t
h7
§
Hold time, address valid after RD1↑ or RD2↓ 3 20 ns
t
d4
§
Delay time, CS valid before WR1↓ or WR2↑ 2 15 ns
t
d5
§
Delay time, address valid before WR1↓ or WR2↑ 2 15 ns
t
d6
Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ 2 80 ns
t
d7
§
Delay time, CS valid to RD1↓ or RD2↑ 3 15 ns
t
d8
§
Delay time, address valid to RD1↓ or RD2↑ 3 15 ns
t
d9
Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ 3 80 ns
§
Only applies when ADS is low.
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