OX16PCI954技术手册：高性能UART与PCI控制器

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"OX16PCI954是一款由Oxford Semiconductor公司生产的多功能PCI控制器，主要特点是集成了四个16C950高性能UART通道、8/32位本地总线过桥、IEEE1284 EPP并行端口等功能。这款设备完全符合PCI 2.2标准和PCI电源管理1.0规范，适用于硬件设计和开发领域。" 本文档详细介绍了OX16PCI954的技术特性，以下是关键点的解析： 1. **16C950 UART通道**：OX16PCI954拥有四个独立的16C950 UART（通用异步接收发送器）通道，这是一种高速UART，与16C550类型的设备软件兼容。这种UART支持高达15Mbps的异步模式波特率和60Mbps的外部单时钟模式波特率。 2. **8/32位本地总线过桥**：该设备允许数据在8位或32位本地总线与PCI总线之间无损传输，提供高效的数据通信路径。 3. **IEEE1284 EPP并行端口**：支持IEEE1284扩展并行端口协议，用于连接各种外设，如打印机和其他需要高速并行通信的设备。 4. **PCI兼容性**：作为多功能目标PCI控制器，OX16PCI954遵循PCI 2.2标准，确保与广泛使用的PCI接口兼容，并且符合PCI电源管理1.0规范，优化了能源效率。 5. **流控制**：支持自动的在带（In-band）和离带（Out-of-band）流控制。通过可编程的Xon/Xoff机制双向控制数据传输，同时使用CTS#/RTS#和/或DSR#/DTR#信号进行硬件流控制。 6. **FIFO中断和自动流控制**：每个UART都配备128字节深度的接收器和发射器FIFO，可以设定任意触发级别以触发中断，并自动执行在带和离带的流控制。 7. **红外（IrDA）功能**：具备红外接收和发射操作能力，可以用于红外数据通信。 8. **9位数据帧格式**：除了传统的5、6、7和8位数据帧格式，还支持9位数据帧，增加了数据传输的灵活性。 9. **多功能I/O引脚**：提供12个可配置的多功能输入/输出引脚，可根据需求设置为不同功能，增强设备的适应性。这些特性使得OX16PCI954成为硬件设计师在构建嵌入式系统、工业控制设备以及需要高级串行通信功能的项目中的理想选择。其强大的流控制和灵活的数据格式支持，确保了数据传输的稳定性和可靠性。

Data Sheet Revision 1.3 Page 12

OX16PCI954

OXFORD SEMICONDUCTOR LTD.

Note 1: Direction key:

I Input

IU Input with internal pull-up

O Output

I/O Bi-directional

OD Open drain

NC No connect

Z High impedance

P_I PCI input

P_O PCI output

P_I/O PCI bi-directional

P_OD PCI open drain

G Ground

V 5.0V power

Note 2: Power & Ground

There are two GND and two VDD rails internally. One set of rails supply power and ground to output buffers while in switching

state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail).

The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF

radiation from the chip. Further precaution is taken by segmenting the GND and VDD AC rails to isolate the PCI, Local Bus and

UART pins.

Data Sheet Revision 1.3 Page 13

OX16PCI954

OXFORD SEMICONDUCTOR LTD.

5 CONFIGURATION & OPERATION

The OX16PCI954 is a multi-function, target-only PCI

device, compliant with the PCI Local Bus Specification,

Revision 2.2 and PCI Power Management Specification,

Revision 1.0.

The OX16PCI954 affords maximum configuration flexibility

by treating the internal UARTs, Local bus and the parallel

port as separate logical functions. Each function has its

own configuration space and is therefore recognised and

configured by the PCI BIOS seperately. The functions

used are configured by the Mode[1:0] pins as shown in

Table 3.

The OX16PCI954 is configured by system start-up

software during the bootstrap process that follows bus

reset. The system scans the bus and reads the vendor and

device identification codes from any devices it finds. It then

loads device-driver software according to this information

and configures the I/O, memory and interrupt resources.

Device drivers can then access the functions at the

assigned addresses in the usual fashion, with the improved

data throughput provided by PCI.

Each function operates as though it was a separate device;

however there are a set of Local configuration registers

that can be used to enable signals and interrupts, configure

timings, and improve the efficiency of multi-port drivers.

This architecture enables separate drivers to be installed

for each function. Generic port drivers can be hooked to

use the functions individually, or more efficient multi-port

drivers can hook both functions, accessing the Local

Configuration Registers from either.

All registers default after reset to suitable values for typical

applications such a 4/8 port serial, or combo 4-port serial/1-

port parallel add-in cards. However, all identification,

control and timing registers can be redefined using an

optional serial EEPROM.

Mode [1:0] Configuration

00 Function 0 is Quad UART, Function 1 is 8-bit local bus

01 Function 0 is Quad UART, Function 1 is parallel port

10 Function 0 is Quad UART, Function 1 is unusable as the local bus pins are used to assign Subsystem

ID and Subsystem Vendor ID to function 0

11 Function 0 is unusable, Function 1 is 32-bit local bus

Table 3: Mode configuration

Data Sheet Revision 1.3 Page 14

OX16PCI954

OXFORD SEMICONDUCTOR LTD.

6 PCI TARGET CONTROLLER

6.1 Operation

The OX16PCI954 responds to the following PCI

transactions:-

• Configuration access: The OX16PCI954 responds to

type 0 configuration reads and writes if the IDSEL

signal is asserted and the bus address is selecting the

configuration registers for function 0 or 1. The device

will respond to the configuration transaction by

asserting DEVSEL#. Data transfer then follows. Any

other configuration transaction will be ignored by the

OX16PCI954.

• IO reads/writes: The address is compared with the

addresses reserved in the I/O Base Address Registers

(BARs). If the address falls within one of the assigned

ranges, the device will respond to the IO transaction

by asserting DEVSEL#. Data transfer follows this

address phase. For the UARTs and 8-bit Local Bus

controller, only byte accesses are possible. For IO

accesses to these regions, the controller compares

AD[1:0] with the byte-enable signals as defined in the

PCI specification. The access is always completed;

however if the correct BE signal is not present the

transaction will have no effect

• Memory reads/writes: These are treated in the same

way as I/O transactions, except that the memory

ranges are used. Memory access to single-byte

regions is always expanded to DWORDs in the

OX16PCI954. In other words, OX16PCI954 reserves

a DWORD per byte in single-byte regions. The device

allows the user to define the active byte lane using

LCC[4:3] so that in Big-Endian systems the hardware

can swap the byte lane automatically. For Memory

mapped access in single-byte regions, the

OX16PCI954 compares the asserted byte-enable with

the selected byte-lane in LCC[4:3] and completes the

operation if a match occurs, otherwise the access will

complete normally on the PCI bus, but it will have no

effect on either the internal UARTs or the local bus

controller.

• All other cycles (64-bit, special cycles, reserved

encoding etc.) are ignored.

The OX16PCI954 will complete all transactions as

disconnect-with-data, ie the device will assert the STOP#

signal alongside TRDY#, to ensure that the Bus Master

does not continue with a burst access. The exception to

this is Retry, which will be signalled in response to any

access while the OX16PCI954 is reading from the serial

EEPROM.

The OX16PCI954 performs medium-speed address

decoding as defined by the PCI specification. It asserts the

DEVSEL# bus signal two clocks after FRAME# is first

sampled low on all bus transaction frames which address

the chip. The internal UARTs are accessed with zero wait

states inserted. Fast back-to-back transactions are

supported by the OX16PCI954 as a target, so a bus master

can perform faster sequences of write transactions to the

UARTs or local bus when an inter-frame turn-around cycle

is not required.

The device supports any combination of byte-enables to

the PCI Configuration Registers, the Local Configuration

registers (see Base Address 2 and 3) and the Local Bus

controller in 32-bit mode. If a byte-enable is not asserted,

that byte is unaffected by a write operation and undefined

data is returned upon a read.

The OX16PCI954 performs parity generation and checking

on all PCI bus transactions as defined by the standard.

Note this is entirely unrelated to serial data parity which is

handled within the UART functional modules themselves. If

a parity error occurs during the PCI bus address phase, the

device will report the error in the standard way by asserting

the SERR# bus signal. However if that address/command

combination is decoded as a valid access, it will still

complete the transaction as though the parity check was

correct.

The OX16PCI954 does not support any kind of caching or

data buffering in addition to that already provided within the

UARTs by the transmit and receive data FIFOs. In general,

registers in the UARTs and on the local bus can not be pre-

fetched because there may be side-effects on read.

6.2 Configuration space

The OX16PCI954 is a dual-function device, where each

logical function has its own configuration space. All

required fields in the standard header are implemented,

plus the Power Management Extended Capability register

set. The format of the configuration space is shown in

Table 4 overleaf.

In general, writes to any registers that are not implemented

are ignored, and all reads from unimplemented registers

return 0.

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