LPC1759系列ARMCortex-M3微控制器技术详解

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"LPC1759_58_56_54_52_51.pdf 是一系列基于ARMCortex-M3内核的微控制器，适用于嵌入式应用，具有高度集成和低功耗特性。" 这些微控制器系列，包括LPC1759、LPC1758、LPC1756、LPC1754、LPC1752和LPC1751，主要由NXP半导体公司设计和制造。它们的核心是先进的ARMCortex-M3处理器，提供了一系列系统增强功能，如增强的调试特性以及更高级别的支持块集成。 ARMCortex-M3处理器运行在高达100MHz的频率（LPC1759则可达到120MHz），采用三级流水线结构，利用哈佛架构，拥有独立的本地指令和数据总线，以及一个用于外设的第三总线。其内部预取单元支持预测分支，提高了处理器的性能和响应速度。在LPC1759/58/56/54/52/51的外围设备配置上，它们提供了丰富的接口和功能： 1. 内置闪存存储空间可达512KB，数据内存最高64KB。 2. 集成了以太网MAC模块，可以实现网络通信。 3. 支持USB设备、主机和OTG（On-The-Go）接口，满足多种USB连接需求。 4. 具有8通道通用DMA（Direct Memory Access）控制器，提高数据传输效率。 5. 包含4个UART（通用异步收发传输器），用于串行通信。 6. 提供2个CAN（Controller Area Network）通道，用于汽车和其他工业环境的高速通信。 7. 设有2个SSP（Synchronous Serial Port）控制器，兼容SPI（Serial Peripheral Interface）接口。 8. 2个I2C总线接口，用于与各种I2C兼容设备通信。 9. 2输入2输出的I2S（Inter-IC Sound）总线接口，适用于音频设备的连接。 10. 6通道12位ADC（Analog-to-Digital Converter），用于将模拟信号转换为数字信号。 11. 10位DAC（Digital-to-Analog Converter），用于将数字信号转换为模拟信号。 12. 电机控制PWM（Pulse Width Modulation）模块，方便电机控制应用。 13. 四象限编码器接口，用于编码器信号的处理。 14. 还包括4个其他未具体说明的功能或接口。这些特性使得LPC1759/58/56/54/52/51微控制器系列适用于广泛的嵌入式系统设计，如工业控制、智能家居、物联网设备、车载电子设备、自动化系统等，它们强大的处理能力和丰富的外设选项使得开发者能够构建高效、低功耗的解决方案。

Product data sheet Rev. 8 — 9 August 2012 13 of 76

NXP Semiconductors

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus (see Figure 1

). The I-code and D-code core buses are faster than the

system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus

dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of

two core buses allows for simultaneous operations if concurrent operations target different

devices.

The LPC1759/58/56/54/52/51 use a multi-layer AHB matrix to connect the ARM

Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes

performance by allowing peripherals that are on different slaves ports of the matrix to be

accessed simultaneously by different bus masters.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,

interruptable/continuable multiple load and store instructions, automatic state save and

restore for interrupts, tightly integrated interrupt controller with wakeup interrupt controller,

and multiple core buses capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual that can be found on official ARM website.

7.3 On-chip flash program memory

The LPC1759/58/56/54/52/51 contain up to 512 kB of on-chip flash memory. A new

two-port flash accelerator maximizes performance for use with the two fast AHB-Lite

buses.

7.4 On-chip SRAM

The LPC1759/58/56/54/52/51 contain a total of up to 64 kB on-chip static RAM memory.

This includes the main 32/16/8 kB SRAM, accessible by the CPU and DMA controller on a

higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a

separate slave port on the AHB multilayer matrix.

This architecture allows CPU and DMA accesses to be spread over three separate RAMs

that can be accessed simultaneously.

7.5 Memory Protection Unit (MPU)

The LPC1759/58/56/54/52/51 have a Memory Protection Unit (MPU) which can be used

to improve the reliability of an embedded system by protecting critical data within the user

application.

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Product data sheet Rev. 8 — 9 August 2012 15 of 76

NXP Semiconductors

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 microcontroller

Fig 3. LPC1759/58/56/54/52/51 memory map

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4002 C000

0x4003 4000

0x4003 0000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 C000

0x4006 0000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

APB1 peripherals

0x4008 0000

0x4008 8000

0x4008 C000

0x4009 0000

0x4009 4000

0x4009 8000

0x4009 C000

0x400A 0000

0x400A 4000

0x400A 8000

0x400A C000

0x400B 0000

0x400B 4000

0x400B 8000

0x400B C000

0x400C 0000

0x400F C000

0x4010 0000

SSP0

DAC

(3)

timer 2

timer 3

UART2

UART3

reserved

I2S

(1)

I2C2

1 - 0 reserved

reserved

repetitive interrupt timer

reserved

motor control PWM

30 - 16 reserved

system control31

reserved

32 kB local static RAM (LPC1759/8)

reserved

private peripheral bus

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x0000 8000

0x1000 4000

16 kB local static RAM (LPC1756/4/2)

0x1000 2000

8 kB local static RAM (LPC1751)

0x1000 0000

0x1000 8000

0x1FFF 0000

0x1FFF 2000

0x2008 0000

0x2008 4000

0x2200 0000

0x200A 0000

0x2009 C000

0x2400 0000

0x4000 0000

0x4008 0000

0x4010 0000

0x4200 0000

0x4400 0000

0x5000 0000

0x5020 0000

0xE000 0000

0xE010 0000

0xFFFF FFFF

reserved

GPIO

reserved

APB0 peripherals

AHB peripherals

APB1 peripherals

AHB SRAM bit-band alias addressing

peripheral bit-band alias addressing

16 kB AHB SRAM1 (LPC1759/8)

0x2007 C000

16 kB AHB SRAM0 (LPC1759/8/6/4)

LPC1759/58/56/54/52/51 memory space

32 kB on-chip flash (LPC1751)

0x0001 0000

64 kB on-chip flash (LPC1752)

0x0002 0000

128 kB on-chip flash (LPC1754)

0x0004 0000

256 kB on-chip flash (LPC1756)

0x0008 0000

512 kB on-chip flash (LPC1759/8)

QEI

APB0 peripherals

WDT

timer 0

timer 1

UART0

UART1

reserved

SPI

RTC + backup registers

GPIO interrupts

pin connect

SSP1

ADC

CAN AF RAM

CAN AF registers

CAN common

CAN1

CAN2

(1)

22 - 19 reserved

I2C1

31 - 24 reserved

PWM1

8 kB boot ROM

0x0000 0000

0x0000 0400

active interrupt vectors

+ 256 words

I-code/D-code

memory space

002aae154

(1)

LPC1759/58/56 only

(2)

LPC1758 only

(3)

LPC1759/58/56/54 only

0x5000 0000

0x5000 4000

0x5000 8000

0x5000 C000

0x5020 0000

0x5001 0000

AHB peripherals

Ethernet controller

(2)

USB controller

reserved

127- 4 reserved

GPDMA controller

Product data sheet Rev. 8 — 9 August 2012 16 of 76

NXP Semiconductors

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 microcontroller

7.7 Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

7.7.1 Features

• Controls system exceptions and peripheral interrupts

• In the LPC1759/58/56/54/52/51, the NVIC supports 33 vectored interrupts

• 32 programmable interrupt priority levels, with hardware priority level masking

• Relocatable vector table

• Non-Maskable Interrupt (NMI)

• Software interrupt generation

7.7.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any pin on Port 0 and Port 2 (total of 30 pins) regardless of the selected function, can be

programmed to generate an interrupt on a rising edge, a falling edge, or both.

7.8 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or

no resistor enabled.

7.9 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected

LPC1759/58/56/54/52/51 peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. The source and

destination areas can each be either a memory region or a peripheral, and can be

accessed through the AHB master. The GPDMA controller allows data transfers between

the USB and Ethernet (LPC1758 only) controllers and the various on-chip SRAM areas.

The supported APB peripherals are SSP0/1, all UARTs, the I

S-bus interface, the ADC,

and the DAC. Two match signals for each timer can be used to trigger DMA transfers.

Remark: Note that the DAC is not available on the LPC1752/51, and the I

S-bus interface

is not available on the LPC1754/52/51.

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