利用高性能计算提升效率：RISC架构与优化

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"《高性能计算（RISC架构、优化与基准测试）》" 该书籍主要探讨了在现代计算机科学中，随着桌面级计算能力的飞速提升，如何利用高性能计算来应对不断增长的计算需求。作者Charles Severance和Kevin Dowd深入浅出地介绍了高性能计算的各个方面，旨在帮助读者理解如何在现有硬件基础上优化性能并实现更高效的计算。标题中的“High Performance Computing”是指利用先进的计算技术来处理大规模和复杂问题的领域。它关注如何在有限的时间内提高计算效率，这与传统的计算机性能提升策略不同，后者更多依赖于硬件的升级。 “RISC Architectures”指的是精简指令集计算机架构，这种架构设计通常拥有更简单的指令集，从而能够更快地执行指令，提高处理器速度。RISC架构在高性能计算中占据重要地位，因为它们能够更有效地处理大量数据。描述中提到，尽管现代个人电脑的性能已经超过了十年前的超级计算机，但性能优化仍然是一个关键问题。这是因为计算需求总是在增长，无论是科学研究、大数据分析还是人工智能，都需要在有限的资源下实现更高的计算效率。书中涵盖的“Optimization & Benchmarks”意味着内容会涉及代码优化技巧，如消除冗余、循环优化等，以及性能基准测试，通过比较不同算法或配置的性能来确定最佳实践。标签中列出的“Charles Severance, Kevin Dowd O'Reilly”表明了作者和出版商的身份，Charles Severance和Kevin Dowd是本书的作者，O'Reilly是知名的科技图书出版公司，其出版的书籍通常具有权威性和深度。书的部分内容包括现代计算机架构、内存管理、浮点数运算、编译器的作用、软件调优、时间测量与分析、并行处理的理解和编程方法等内容。这些章节旨在提供一个全面的视角，帮助读者理解和应用高性能计算的原理和技术。《高性能计算（RISC架构、优化与基准测试）》是一本关于如何在当前硬件环境下最大化计算效率的实用指南，适合对高性能计算感兴趣的科研人员、软件工程师和学生阅读。通过学习书中的知识，读者可以更好地掌握如何利用RISC架构进行优化，并通过编程技巧和并行处理策略提升计算性能。

CHAPTER 1. MODERN COMPUTER ARCHITECTURES

The actual cache architecture has had to change as the cycle time of the processors has improved. The

processors are so fast that o-chip SRAM chips are not even fast enough. This has lead to a multilevel cache

approach with one, or even two, levels of cache implemented as part of the processor. Table 1.1 shows the

approximate speed of accessing the memory hierarchy on a 500-MHz DEC 21164 Alpha.

Registers 2 ns

L1 On-Chip 4 ns

L2 On-Chip 5 ns

L3 O-Chip 30 ns

Memory 220 ns

Table 1.1

: Memory Access Speed on a DEC 21164 Alpha

When every reference can be found in a cache, you say that you have a 100% hit rate. Generally, a hit

rate of 90% or better is considered good for a level-one (L1) cache. In level-two (L2) cache, a hit rate of

above 50% is considered acceptable. Below that, application performance can drop o steeply.

One can characterize the average read performance of the memory hierarchy by examining the probability

that a particular load will be satised at a particular level of the hierarchy. For example, assume a memory

architecture with an L1 cache speed of 10 ns, L2 speed of 30 ns, and memory speed of 300 ns. If a memory

reference were satised from L1 cache 75% of the time, L2 cache 20% of the time, and main memory 5% of

the time, the average memory performance would be:

(0.75 * 10 ) + ( 0.20 * 30 ) + ( 0.05 * 300 ) = 28.5 ns

You can easily see why it's important to have an L1 cache hit rate of 90% or higher.

Given that a cache holds only a subset of the main memory at any time, it's important to keep an index of

which areas of the main memory are currently stored in the cache. To reduce the amount of space that must

be dedicated to tracking which memory areas are in cache, the cache is divided into a number of equal sized

slots known as

lines

. Each line contains some number of sequential main memory locations, generally four

to sixteen integers or real numbers. Whereas the data within a line comes from the same part of memory,

other lines can contain data that is far separated within your program, or perhaps data from somebody

else's program, as in Figure 1.1 (Cache lines can come from dierent parts of memory). When you ask for

something from memory, the computer checks to see if the data is available within one of these cache lines.

If it is, the data is returned with a minimal delay. If it's not, your program may be delayed while a new line

is fetched from main memory. Of course, if a new line is brought in, another has to be thrown out. If you're

lucky, it won't be the one containing the data you are just about to need.

CHAPTER 1. MODERN COMPUTER ARCHITECTURES

DO I=1,1000000, 8

SUM = SUM + A(I)

END DO

This code would experience the same number of cache misses as the previous loop, and the same amount of

data would be loaded into the cache. However, the program needs only one of the eight 32-bit words loaded

into cache. Even though this program performs one-eighth the additions of the previous loop, its elapsed

time is roughly the same as the previous loop because the memory operations dominate performance.

While this example may seem a bit contrived, there are several situations in which non-unit strides occur

quite often. First, when a FORTRAN two-dimensional array is stored in memory, successive elements in the

rst column are stored sequentially followed by the elements of the second column. If the array is processed

with the row iteration as the inner loop, it produces a unit-stride reference pattern as follows:

REAL*4 A(200,200)

DO J = 1,200

DO I = 1,200

SUM = SUM + A(I,J)

END DO

Interestingly, a FORTRAN programmer would most likely write the loop (in alphabetical order) as follows,

producing a non-unit stride of 800 bytes between successive load operations:

REAL*4 A(200,200)

DO I = 1,200

DO J = 1,200

SUM = SUM + A(I,J)

END DO

Because of this, some compilers can detect this suboptimal loop order and reverse the order of the loops to

make best use of the memory system. As we will see in Section 1.2.1, however, this code transformation may

produce dierent results, and so you may have to give the compiler permission to interchange these loops

in this particular example (or, after reading this book, you could just code it properly in the rst place).

while ( ptr != NULL ) ptr = ptr-

next;

The next element that is retrieved is based on the contents of the current element. This type of loop bounces

all around memory in no particular pattern. This is called

pointer chasing

and there are no good ways to

improve the performance of this code.

A third pattern often found in certain types of codes is called gather (or scatter) and occurs in loops

such as:

SUM = SUM + ARR ( IND(I) )

where the IND array contains osets into the ARR array. Again, like the linked list, the exact pattern of

memory references is known only at runtime when the values stored in the IND array are known. Some

special-purpose systems have special hardware support to accelerate this particular operation.

1.1.5 Cache Organization

The process of pairing memory locations with cache lines is called

mapping

. Of course, given that a cache is

smaller than main memory, you have to share the same cache lines for dierent memory locations. In caches,

each cache line has a record of the memory address (called the

tag

) it represents and perhaps when it was

last used. The tag is used to track which area of memory is stored in a particular cache line.

The way memory locations (tags) are mapped to cache lines can have a benecial eect on the way your

program runs, because if two heavily used memory locations map onto the same cache line, the miss rate

will be higher than you would like it to be. Caches can be organized in one of several ways: direct mapped,

fully associative, and set associative.

1.1.5.1 Direct-Mapped Cache

Direct mapping, as shown in Figure 1.2 (Many memory addresses map to the same cache line), is the simplest

algorithm for deciding how memory maps onto the cache. Say, for example, that your computer has a 4-KB

cache. In a direct mapped scheme, memory location 0 maps into cache location 0, as do memory locations

4K, 8K, 12K, etc. In other words, memory maps onto the cache size. Another way to think about it is to

imagine a metal spring with a chalk line marked down the side. Every time around the spring, you encounter

the chalk line at the same place modulo the circumference of the spring. If the spring is very long, the chalk

line crosses many coils, the analog being a large memory with many locations mapping into the same cache

line.

Problems occur when alternating runtime memory references in a direct-mapped cache point to the same

cache line. Each reference causes a cache miss and replaces the entry just replaced, causing a lot of overhead.

The popular word for this is

thrashing

. When there is lots of thrashing, a cache can be more of a liability

than an asset because each cache miss requires that a cache line be relled  an operation that moves more

data than merely satisfying the reference directly from main memory. It is easy to construct a pathological

case that causes thrashing in a 4-KB direct-mapped cache:

This content is available online at <http://cnx.org/content/m32722/1.3/>.

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