高性价比选择：台湾合泰32位MCU HT32F12365/66

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"32位合泰单片机，尤其是型号为HT32F12365的芯片，提供了一种在STM32价格波动时的高性价比选择。这款微控制器基于32位Arm Cortex-M3内核，集成了丰富的功能模块，包括大容量的闪存和SRAM，高速ADC，多种通信接口以及先进的定时器和安全特性。" 合泰（Holtek）的HT32F12365是一款高性能、低功耗的32位微控制器，采用了Arm公司的Cortex-M3处理器核心，具有出色的处理能力和能效比。该芯片提供了高达256KB的闪存和128KB的SRAM，能满足复杂应用的存储需求。此外，它还配备了1MSPS（百万样本每秒）的模数转换器（ADC），适用于需要高精度模拟信号处理的场合。在接口方面，HT32F12365包含了多种通用接口，如USART（通用同步异步收发传输器）、UART（通用异步收发传输器）、SPI（串行外围设备接口）、I2C（集成电路间通信）和I2S（集成串行音频接口）。这些接口可以方便地连接各种外设和传感器，实现数据通信。同时，该芯片还集成了MCTM（电机控制定时器）、GPTM（PWM生成和捕获定时器）、BFTM（基本功能定时器）等定时器单元，适合电机控制和其他时间敏感的应用。安全特性方面，HT32F12365包含了SCI（智能卡接口）、CRC（循环冗余校验）、RTC（实时时钟）、WDT（看门狗定时器）以及AES（高级加密标准）等，确保了数据的完整性和系统的稳定性。其中，AES加密功能对于需要保护数据安全的应用尤其重要。此外，通过EBI（外部总线接口）和CSIF（彩色串行接口）可扩展外部存储和显示设备，而USB2.0FS（全速）接口则支持与PC或其他USB设备的高速通信。总体而言，HT32F12365是针对成本敏感且功能需求丰富的嵌入式应用设计的，其全面的功能集和高性价比使得它成为STM32之外的一个可靠替代选项，尤其适用于工业控制、智能家居、物联网设备等领域的开发。

Rev. 1.00 10 of 56 November 07, 2017

32-Bit Arm

Cortex

-M3 MCU

HT32F12365/HT32F12366/HT32F22366

Features

I/O Ports – GPIO

▆

Up to 80 GPIOs

▆

Port A, B, C, D, E are mapped as 16 external interrupts – EXTI

▆

Almost I/O pins are congurable output driving current

There are up to 80 General Purpose I/O pins, GPIO, named from PA0 ~ PA15 to PE0 ~ PE15 for

the implementation of logic input/output functions. Each of the GPIO ports has a series of related

control and conguration registers to maximize exibility and to meet the requirements of a wide

range of applications.

The GPIO ports are pin-shared with other alternative functions to obtain maximum functional

flexibility on the package pins. The GPIO pins can be used as alternative functional pins by

conguring the corresponding registers regardless of the input or output pins.

The external interrupts on the GPIO pins of the device have related control and configuration

registers in the External Interrupt Control Unit, EXTI.

Motor Control Timer – MCTM

▆

Two 16-bit up, down, up/down auto-reload counters

▆

16-bit programmable prescaler allowing division of the counter clock frequency by any factor

between 1 and 65536

▆

Input Capture function

▆

Compare Match Output

▆

PWM waveform generation with edge aligned and center-aligned Counting Modes

▆

Single Pulse Mode Output

▆

Complementary Outputs with programmable dead-time insertion

▆

Encoder interface controller with two inputs using quadrature decoder

▆

Supports 3-phase motor control and hall sensor interface

▆

Brake input to force the timer’s output signals into a reset or xed condition

The Motor Control Timer consists of a single 16-bit up/down counter; four 16-bit CCRs (Capture/

Compare Registers), single 16-bit counter-reload register (CRR), single 8-bit repetition counter

and several control/status registers. It can be used for a variety of purposes including measuring

the pulse widths of input signals or generating output waveforms such as compare match outputs,

PWM outputs or complementary PWM outputs with dead-time insertion. The MCTM supports an

Encoder interface controller to an incremental encoder with two inputs. The MCTM is capable of

offering full functional support for motor control, hall sensor interfacing and brake input.

Rev. 1.00 11 of 56 November 07, 2017

32-Bit Arm

Cortex

-M3 MCU

HT32F12365/HT32F12366/HT32F22366

Features

PWM Generation and Capture Timers – GPTM

▆

Two 16-bit up, down, up/down auto-reload counters

▆

16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

▆

Input Capture function

▆

Compare Match Output

▆

PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

▆

Single Pulse Mode Output

▆

Encoder interface controller with two inputs using quadrature decoder

The General Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare

Registers (CCRs), one 16-bit Counter Reload Register (CRR) and several control/status registers.

They can be used for a variety of purposes including general time measurement, input signal pulse

width measurement, output waveform generation such as single pulse generation, or PWM output

generation. The GPTM supports an Encoder Interface using a decoder with two inputs.

Basic Function Timer – BFTM

▆

Two 32-bit compare/match count-up counters - no I/O control features

▆

One shot mode – counting stops after a match condition

▆

Repetitive mode – restart counter after a match condition

The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals

and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,

repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare

match event occurs. The BFTM also supports a one shot mode which forces the counter to stop

counting when a compare match event occurs.

Watchdog Timer – WDT

▆

12-bit down counter with 3-bit prescaler

▆

Interrupt or reset event for the system

▆

Programmable watchdog timer window function

▆

The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due to

software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT counter value

and a WDT protection mechanism. The Watchdog Timer can be operated in an interrupt mode or

a reset mode. The Watchdog Timer will generate an interrupt or a reset when the counter counts

down and reaches a zero value. If the software does not reload the counter value before a Watchdog

Timer underow occurs, an interrupt or a reset will be generated when the counter underows. In

addition, an interrupt or reset is also generated if the software reloads the counter when the counter

value is greater than or equal to the WDT delta value. This means the counter must be reloaded

within a limited timing window using a specific method. The Watchdog Timer counter can be

stopped while the processor is in the debug mode. There is a register write protect function which

can be enabled to prevent it from changing the Watchdog Timer conguration unexpectedly.

Rev. 1.00 12 of 56 November 07, 2017

32-Bit Arm

Cortex

-M3 MCU

HT32F12365/HT32F12366/HT32F22366

Features

Real Time Clock – RTC

▆

32-bit up-counter with a programmable prescaler

▆

Alarm function

▆

Interrupt and Wake-up event

The Real Time Clock, RTC for short, includes an APB interface, a 32-bit count-up counter, a

control register, a prescaler, a compare register and a status register. Most of the RTC circuits are

located in the Backup Domain except for the APB interface. The APB interface is located in the

DD15

power domain. Therefore, it is necessary to be isolated from the ISO signal that comes from

the power control unit when the V

DD15

power domain is powered off, that is when the device enters

the Power-Down mode. The RTC counter is used as a wakeup timer to generate a system resume

signal from the Power-Down mode.

Inter-integrated Circuit – I

▆

Supports both master and slave modes with a frequency of up to 1 MHz

▆

Provide an arbitration function and clock synchronization

▆

Supports 7-bit and 10-bit addressing modes and general call addressing

▆

Supports slave multi-addressing mode with maskable address

The I

C Module is an internal circuit allowing communication with an external I

C interface which

is an industry standard two line serial interface used for connection to external hardware. These

two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I

C module

provides three data transfer rates: (1) 100 kHz in the Standard mode, (2) 400 kHz in the Fast mode

and (3) 1 MHz in the Fast mode plus mode. The SCL period generation register is used to setup

different kinds of duty cycle implementations for the SCL pulse.

The SDA line which is connected directly to the I

C bus is a bi-directional data line between the

master and slave devices and is used for data transmission and reception. The I

C module also has

an arbitration detect function and clock synchronization to prevent situations where more than one

master attempts to transmit data to the I

C bus at the same time.

Serial Peripheral Interface – SPI

▆

Supports both master and slave mode

▆

Frequency of up to (f

PCLK

/2) MHz for master mode and (f

PCLK

/3) MHz for slave mode

▆

FIFO Depth: 8 levels

▆

Multi-master and multi-slave operation

The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function

in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and

output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device

acts as a master device which controls the data ow using the SEL and SCK signals to indicate the

start of data communication and the data sampling rate. To receive a data byte, the streamed data

bits are latched on a specic clock edge and stored in the data register or in the RX FIFO. Data

transmission is carried out in a similar way but in a reverse sequence. The mode fault detection

provides a capability for multi-master applications.

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