"最新PCIe M.2 1.1协议规范发布"

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PCIe M.2 1.1协议规范是一份由PCI-SIG发布的技术规范文件，其最新版本为PCI Express M.2 Specification Revision 1.1.pdf。该规范旨在为硬件开发者和制造商提供关于PCIe M.2接口的详尽指导，以便他们可以有效地设计、生产和测试满足该规范的硬件设备。本规范于2016年3月7日发布，由PCI-SIG®发布，内容包括有关PCIe M.2接口的物理尺寸、电气规范、传输协议以及兼容性要求等方面的详细信息。 PCIe M.2 1.1协议规范的发布旨在促进和支持更高速、更高效的PCIe M.2硬件设备的开发和生产。该规范的发布为硬件开发者和制造商提供了一个标准化的参考框架，使他们能够更加高效地设计和生产兼容该规范的硬件设备。同时，该规范的发布也有助于确保不同厂家生产的PCIe M.2硬件设备之间的兼容性，从而提高了整个PCIe M.2硬件生态系统的可靠性和稳定性。然而，PCI-SIG在发布PCIe M.2 1.1协议规范时明确声明，他们对于该规范的使用以及规范中包含的信息不承担任何责任并且放弃所有相关的担保和责任。PCI-SIG并不承诺对规范中出现的任何错误进行更新或修正。因此，使用PCIe M.2 1.1协议规范的硬件开发者和制造商需要在使用该规范时自行承担风险，并在实际应用中充分考虑可能出现的错误和问题。在获取PCIe M.2 1.1协议规范的最新版本时，用户需要与PCI-SIG办公室进行联系，以确保获得最新的规范文件。此外，对于规范中的任何疑问或者对PCI-SIG会员资格的申请，用户也可以通过相关渠道进行咨询和反馈。综上所述，PCIe M.2 1.1协议规范是一份由PCI-SIG发布的技术规范文件，其发布旨在促进和支持更高速、更高效的PCIe M.2硬件设备的开发和生产。该规范的发布为硬件开发者和制造商提供了标准化的参考框架，同时也有助于提高整个PCIe M.2硬件生态系统的可靠性和稳定性。然而，在使用该规范时，用户需要自行承担风险，并在实际应用中充分考虑可能出现的错误和问题。PCI-SIG也鼓励用户获取规范的最新版本，并提供相关咨询和反馈渠道，以帮助用户更好地理解和应用该规范。

PCI Express M.2 Specification

PCI Express M.2 Specification | 16

Revision 1.1, March 7, 2016

List of Tables

Table 1. Optional Module Configurations............................................................................................. 27

Table 2. General Tolerance ................................................................................................................. 28

Table 3. Key Location/Pin Block Dimensions for Keys A - F ............................................................... 42

Table 4. Key Location/Pin Block Dimensions for Keys G - M .............................................................. 42

Table 5. RF Connector Physical Characteristics ................................................................................. 65

Table 6. RF Connector Mechanical Requirements .............................................................................. 65

Table 7. RF Connector Electrical Requirements ................................................................................. 66

Table 8. RF Connector Environmental Requirements ......................................................................... 66

Table 9. Recommended Antenna Function Allocation Table............................................................... 67

Table 10. Connector/Module Type Supported Matrix ............................................................................ 70

Table 11. Connector Physical Requirements......................................................................................... 71

Table 12. Connector Environmental Requirements ............................................................................... 72

Table 13. Connector Electrical Requirements ....................................................................................... 72

Table 14. Stand-off Height Descriptor Table.......................................................................................... 94

Table 15. Socket 1 System Interface Signals and Voltage Table ........................................................ 102

Table 16. Power-up CLKREQ# Timings .............................................................................................. 109

Table 17. Power-up Timing Variables .................................................................................................. 111

Table 18. DP_MLDIR Pin Termination ................................................................................................. 113

Table 19. SDIO Reset and Power-up Timing....................................................................................... 114

Table 20. Simple Indicator Protocol for LED States ............................................................................ 120

Table 21. Radio Operational States ..................................................................................................... 121

Table 22. SDIO Based Module Solution Pinouts (Module Key E) ....................................................... 123

Table 23. Display Port Based Module Solution Pinouts (Module Key A) ............................................ 124

Table 24. Socket 1 Module Pinouts (Module Key A-E) ........................................................................ 125

Table 25. Socket 2 System Interface Signal Table .............................................................................. 129

Table 26. GPIO Pin Function Assignment per Port Configuration ....................................................... 138

Table 27. Audio Pin Mode and Function Assignment .......................................................................... 140

Table 28. Antenna Control Pin Mode and Function Assignment ......................................................... 141

Table 29. Socket 2 Module Configuration ............................................................................................ 143

Table 30. Socket 2 Key B SSIC-based WWAN Module Pinouts ......................................................... 145

Table 31. Socket 2 Key B USB3.0-based WWAN Module Pinout ....................................................... 146

Table 32. Socket 2 Key B PCIe-based WWAN Module Pinout ........................................................... 147

Table 33. Socket 2 Key B-M SATA-based SSD Module Pinout .......................................................... 148

Table 34. Socket 2 Key B-M PCIe-based SSD Module Pinout............................................................ 149

Table 35. Socket 2 Key C WWAN Module Pinout ............................................................................... 150

PCI Express M.2 Specification

PCI Express M.2 Specification | 17

Revision 1.1, March 7, 2016

Table 36. Socket 3 System Interface Signal Table .............................................................................. 151

Table 37. Socket 3 SATA-based Module Pinouts (Module Key M) ..................................................... 154

Table 38. Socket 3 PCIe-based Module Pinouts (Module Key M)....................................................... 155

Table 39. BGA SSD System Interface Signal Table ............................................................................ 156

Table 40. DC Specification for 3.3 V Logic Signaling .......................................................................... 163

Table 41. DC Specification for 1.8 V Logic Signaling .......................................................................... 164

Table 42. Power Ramp Timing ............................................................................................................ 166

Table 43. Power Rail Slew Rate .......................................................................................................... 167

Table 44. Key Regulated Power Rail Parameters ............................................................................... 168

Table 45. Key VBAT Power Rail Parameters ...................................................................................... 168

Table 46. Power Rating Table for M.2 Modules with Connectors........................................................ 169

Table 47. Mechanical Key Assignments .............................................................................................. 171

Table 48. Socket 1 Versions ................................................................................................................ 172

Table 49. Display Port Based Socket 1 Pinout Diagram (Mechanical Key A) On Platform ................ 174

Table 50. SDIO Based Socket 1 Pinout Diagram (Mechanical Key E) On Platform ........................... 176

Table 51. Socket 2 Module Configuration Table .................................................................................. 178

Table 52. Socket 2 Pinouts Diagram (Mechanical Key B) On Platform ............................................... 180

Table 53. Socket 2 Pinout Diagram (Mechanical Key C) on Platform ................................................. 182

Table 54. Socket 3 SSD Pinout (Mechanical Key M) On Platform ...................................................... 183

Table 55. Signal Integrity Requirements and Test Procedures for M.2 ............................................... 193

Table 56. Example of Prepared Wire with Plug, Unit: mΩ ................................................................... 205

Table 57. Contact Resistance for the Sample Wires/Plugs, Unit: mΩ ................................................. 206

Table 58. Assumptions for Typical Components and Dissipation........................................................ 207

Table 59. Maximum Dissipation for WWAN Modules .......................................................................... 208

Table 60. Generic Assumptions for Package Designations and Types Expected to

Populate Modules ................................................................................................................ 208

Table 61. Assumptions for Generic System Environments ................................................................. 209

Table 62. Slot Definitions, Systems with Fans ..................................................................................... 210

Table 63. Slot Definitions, Systems without Fans ................................................................................ 210

Table 64. Example Use Case Applicable to Modules for Notebooks .................................................. 213

Table 65. Thermal Design Power Response – Notebook Category .................................................... 217

Table 66. Skin Temperature Limit Assumptions, Notebook ................................................................. 217

Table 67. Skin Temperature Effect of Module Position ....................................................................... 218

Table 68. Use Cases Applicable to Modules for Thin Platform Notebook with Fan ........................... 218

Table 69. Thermal Design Power Response – Thin Platform Notebook with Fan Category ............... 223

Table 70. Skin temperature limit assumptions, Thin platform notebook with Fan ............................... 223

Table 71. Use Cases Applicable to Modules for Tablet without Fan ................................................... 224

Table 72. Thermal Design Power Response—Tablet Category .......................................................... 227

Table 73. Skin Temperature Limit Assumptions, Tablet without Fan .................................................. 228

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