ADV7179：高品质10位视频编码器技术详解

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本文档是关于ADV7179芯片的规格说明书，由Analog Devices公司提供。ADV7179是一款高级视频编码器，专为满足ITU-R BT.601/BT.656标准的PAL/NTSC视频信号处理设计，适用于高质量的10位视频数字-to-analog转换器(DAC)应用。该设备的关键特性包括： 1. **高清晰度视频编码**：支持国际电信联盟（ITU）的BT.601和BT.656标准，确保输出的图像质量和兼容性。 2. **Super Sub-Aliasing Filter (SSAF)**：这是一种先进的滤波技术，旨在减少视频信号中的图像失真，提高画面的清晰度和细节表现。 3. **先进电源管理**：ADV7179具有节能功能，能够优化功耗，延长设备在低功耗模式下的运行时间，对于电池供电或能源效率高的系统尤其重要。 4. **Copy Generation Management System (CGMS)**：允许对视频内容进行合法复制控制，确保版权合规。 5. **宽屏幕信号处理（WSS）**：支持宽屏显示格式，适应现代电视和显示器的多样化需求。 6. **广泛的兼容性**：支持NTSCM、PAL N2、PAL B/D/G/H/I、PAL-M3以及PAL 60等多种标准，适应全球不同地区的电视制式。 7. **高效时钟需求**：只需要一个27MHz的单时钟源，通过×2的过采样技术实现视频编码，简化了电路设计。 8. **专有功能**：对于ADV7174型号，还具备Macrovision 7.1技术，可能涉及到视频版权保护或特定的音频处理功能。 9. **高视频信噪比（SNR）**：达到80分贝，保证了视频信号的纯净度和稳定性。 10. **32位直接数字合成器**：用于精确的视频频率和相位控制，有助于提升信号质量。 ADV7179是一款高性能且具备多种先进特性的视频编码器，广泛应用于电视、消费电子、多媒体设备等对图像质量有严格要求的领域。其设计考虑到了能源效率、兼容性和信号处理能力，是构建高质量视频传输系统的重要组件。在实际应用中，用户应根据具体需求参考文档中的详细参数和限制，以确保系统的最佳性能和合规性。

ADV7174/ADV7179

Rev. A | Page 9 of 52

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

to GND 4 V

Voltage on Any Digital Input Pin GND – 0.5 V to V

+ 0.5 V

Storage Temperature (T

) −65°C to +150°C

Junction Temperature (T

) 150°C

Lead Temperature

Soldering, 10 sec

260°C

Analog Outputs to GND

GND – 0.5 V to V

30°C/W

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability

__________________________________________________

Analog output short circuit to any power supply or common can be of an indefinite duration.

With the exposed metal paddle on the underside of LFCSP soldered to GND on the PCB.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

ADV7174/ADV7179

Rev. A | Page 10 of 52

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

12 13 14 15 16 17

19 20

37 36 3538

40 33 32 3134

REF

DAC A

DAC B

GND

DAC C

BLANK

GND

HSYNC

FIELD/VSYNC

ALSB

LOC

GND

COMP

SDATA

SCLOCK

GND

RESET

GND

TTX

TTXREQ

SET

SCRESET/

RTC

PIN 1

INDICATOR

ADV7174/ADV7179

LFCSP

TOP VIEW

(Not to Scale)

02980-A-005

Figure 5. Pin Configurations

Table 6. Pin Function Descriptions

Mnemonic

Input/

Output

Function

P7–P0 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0). P0 is the LSB.

CLOCK I

TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz

(NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.

HSYNC

I/O

HSYNC

(Modes 1 and 2) Control Signal. This pin may be configured to output (master mode) or accept (slave

mode) sync signals.

FIELD/VSYNC

I/O

Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output

(master mode) or accept (slave mode) these control signals.

BLANK

I/O Video Blanking Control Signal. The pixel inputs are ignored when this is Logic 0. This signal is optional.

SCRESET/RTC I

This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a

subcarrier reset pin, in which case a low-to-high transition on this pin resets the subcarrier to Field 0.

Alternatively, it can be configured as a real-time control (RTC) input.

REF

I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

SET

I A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals.

COMP O

Compensation Pin. Connect a 0.1 µF capacitor from COMP to V

. For optimum dynamic performance in low

power mode, the value of the COMP capacitor can be lowered to as low as 2.2 nF.

DAC A O DAC Output (see Table 13)

DAC B O DAC Output (see Table 13).

DAC C O DAC Output (see Table 13).

SCLOCK I MPU Port Serial Interface Clock Input.

SDATA I/O MPU Port Serial Data Input/Output.

ALSB I TTL Address Input. This signal sets up the LSB of the MPU address.

RESET

This input resets the on-chip timing generator and sets the ADV7174/ADV7179 into default mode. This is NTSC

operation, Timing Slave Mode 0, 8-bit operation, 2× composite out signals. DACs A, B, and C are enabled.

TTX I Teletext Data.

TTXREQ O Teletext Data Request Signal/Defaults to GND when Teletext Not Selected.

P Power Supply (2.8 V or 3.3 V).

GND G Ground Pin.

ADV7174/ADV7179

Rev. A | Page 11 of 52

GENERAL DESCRIPTION

The ADV7174/ADV7179 is an integrated digital video encoder

that converts digital CCIR-601 4:2:2 8-bit component video data

into a standard analog baseband television signal compatible

with worldwide standards.

The on-board SSAF (super sub-alias filter) with extended

luminance frequency response and sharp stop-band attenuation

enables studio quality video playback on modern TVs, giving

optimal horizontal line resolution.

An advanced power management circuit enables optimal con-

trol of power consumption in both normal operating modes

and in power-down or sleep modes.

The ADV7174/ADV7179 supports both PAL and NTSC square

pixel operation. The parts incorporate WSS and CGMS-A data

control generation.

The output video frames are synchronized with the incoming

data timing reference codes. Optionally, the encoder accepts

(and can generate)

HSYNC

VSYNC

, and FIELD timing signals.

These timing signals can be adjusted to change pulse width and

position while the part is in the master mode. The encoder

requires a signal two times the pixel rate (27 MHz) clock for

standard operation. Alternatively, the encoder requires a

24.5454 MHz clock for NTSC or 29.5 MHz clock for PAL

square pixel mode operation. All internal timing is generated

on-chip.

A separate Teletext port enables the user to directly input

Teletext data during the vertical blanking interval.

The ADV7174/ADV7179 modes are set up over a 2-wire serial

bidirectional port (I

C compatible) with two slave addresses.

The ADV7174/ADV7179 is packaged in a 40-lead 6 mm × 6 mm

LFCSP package.

DATA PATH DESCRIPTION

For PAL B/D/G/H/I/M/N and NTSC M and N modes, YCrCb

4:2:2 data is input via the CCIR-656 compatible pixel port at a

27 MHz data rate. The pixel data is demultiplexed to form three

data paths. Y typically has a range of 16 to 235, and Cr and Cb

typically have a range of 128 ± 112; however, it is possible to

input data from 1 to 254 on both Y, Cb, and Cr. The ADV7174/

ADV7179 supports PAL (B/D/G/H/I/M/N) and NTSC (with

and without pedestal) standards. The appropriate SYNC,

BLANK

and burst levels are added to the YCrCb data. Macrovision Anti-

taping (ADV7174 only), closed-captioning, and Teletext levels

are also added to Y and the resultant data is interpolated to a

rate of 27 MHz. The interpolated data is filtered and scaled by

three digital FIR filters.

The U and V signals are modulated by the appropriate subcarrier

sine/cosine phases and added together to make up the chromi-

nance signal. The luma (Y) signal can be delayed 1–3 luma

cycles (each cycle is 74 ns) with respect to the chroma signal.

The luma and chroma signals are then added together to make

up the composite video signal. All edges are slew rate limited.

The YCrCb data is also used to generate RGB data with

appropriate SYNC and

BLANK

levels. The RGB data is in

synchronization with the composite video output. Alternatively,

analog YPbPr data can be generated instead of RGB data.

The three l0-bit DACs can be used to output:

• Composite Video + Composite Video

• S-Video + Composite Video

• YPrPb Video

• SCART RGB Video

Alternatively, each DAC can be individually powered off if not

required.

Video output levels are illustrated in Appendix 6.

INTERNAL FILTER RESPONSE

The Y filter supports several different frequency responses,

including two low-pass responses, two notch responses, an

extended (SSAF) response, a CIF response, and a QCIF

response. The UV filter supports several different frequency

responses, including four low-pass responses, a CIF response,

and a QCIF response. These can be seen in Table 7 and Table 8

and Figure 6 to Figure 18.

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