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DP83848IVVXNOPB工业级以太网PHY芯片数据手册
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更新于2024-07-16
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"DP83848IVVXNOPB是一款专为工业温度环境设计的单端口10/100Mbps以太网物理层收发器芯片,其数据手册提供了详尽的技术资料。该芯片具备强大的功能特性,旨在实现低功耗性能,通过多种智能电源管理模式确保在节省能源的同时提高产品可靠性。它支持一系列智能电源状态,允许用户在满足设备运行需求的同时,最大限度地减少能耗。 DP83848I芯片的核心优势之一是内置的25MHz时钟输出,这使得系统设计者能够减少外部组件的数量,从而降低整体解决方案的成本。它的设计优化了电缆长度性能,超越了IEEE标准的要求,这意味着即使在较长的传输距离下也能保持高效稳定的通信。 此外,这款芯片还具有高度的工业级耐用性,能在严苛的工作环境中稳定工作,对于需要在工业自动化、物联网(IoT)、自动化控制等领域应用的设备来说,是非常理想的选型。它支持自动协商功能,可以与不同速率的以太网设备无缝对接,提供灵活的网络连接。 为了方便工程师理解和应用,手册中包含详细的基本电路原理图和封装图,以便于理解芯片内部结构以及如何将其集成到实际的电路板设计中。安全规范、电气参数、操作指南、典型应用示例和故障诊断信息也一应俱全,以确保用户能有效利用这款芯片进行高效、可靠的网络通信设计。 DP83848I以太网PHY芯片是一个集高可靠性、低功耗、成本效益和高性能于一体的解决方案,适合对工业环境下的以太网通信有严格要求的项目。通过深入研究其数据手册,开发人员可以充分利用其特性,提升产品的竞争力和市场适应性。"
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15 www.national.com
DP83848I
1.11 Package Pin Assignments
VBH48A Pin # Pin Name
1 TX_CLK
2 TX_EN
3 TXD_0
4 TXD_1
5 TXD_2
6 TXD_3/SNI_MODE
7 PWR_DOWN/INT
8 TCK
9 TDO
10 TMS
11 TRST#
12 TDI
13 RD -
14 RD +
15 AGND
16 TD -
17 TD +
18 PFBIN1
19 AGND
20 RESERVED
21 RESERVED
22 AVDD33
23 PFBOUT
24 RBIAS
25 25MHz_OUT
26 LED_ACT/COL/AN_EN
27 LED_SPEED/AN1
28 LED_LINK/AN0
29 RESET_N
30 MDIO
31 MDC
32 IOVDD33
33 X2
34 X1
35 IOGND
36 DGND
37 PFBIN2
38 RX_CLK
39 RX_DV/MII_MODE
40 CRS/CRS_DV/LED_CFG
41 RX_ER/MDIX_EN
42 COL/PHYAD0
43 RXD_0/PHYAD1
44 RXD_1/PHYAD2
45 RXD_2/PHYAD3
46 RXD_3/PHYAD4
47 IOGND
48 IOVDD33
VBH48A Pin # Pin Name
www.national.com 16
DP83848I
2.0 Configuration
This section includes information on the various configura-
tion options available with the DP83848I. The configuration
o
ptions described below include:
— Auto-Negotiation
— PHY Address and LEDs
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
—BIST
2.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for
exchanging configuration information between two ends of
a link segment and automatically selecting the highest per-
formance mode of operation supported by both devices.
Fa
st Link Pulse (FLP) Bursts provide the signalling used to
communicate Auto-Negotiation abilities between two
devices at each end of a link segment. For further detail
regarding Auto-Negotiation, refer to Clause 28 of the IEEE
802.3u specification. The DP83848I supports four different
Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),
so the inclusion of Auto-Negotiation ensures that the high-
est performance protocol will be selected based on the
a
dvertised ability of the Link Partner. The Auto-Negotiation
function within the DP83848I can be controlled either by
internal register access or by the use of the AN_EN, AN1
and AN0 pins.
2.1.1 Auto-Negotiation Pin Control
The state of AN_EN, AN0 and AN1 determines whether the
D
P83848I is forced into a specific mode or Auto-Negotia-
tion will advertise a specific ability (or set of abilities) as
g
iven in Table 1. These pins allow configuration options to
be selected without requiring internal register access.
The state of AN_EN, AN0 and AN1, upon power-up/reset,
d
etermines the state of bits [8:5] of the ANAR register.
The Auto-Negotiation function selected at power-up or
r
eset can be changed at any time by writing to the Basic
Mode Control Register (BMCR) at address 0x00h.
2.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83848I transmits
t
he abilities programmed into the Auto-Negotiation Adver-
tisement register (ANAR) at address 04h via FLP Bursts.
An
y combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and
Full Duplex modes may be selected.
Auto-Negotiation Priority Resolution:
— (1) 100BASE-TX Full Duplex (Highest Priority)
— (2) 100BASE-TX Half Duplex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h
provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is dis-
abled, the Speed Selection bit in the BMCR controls
s
witching between 10 Mb/s or 100 Mb/s operation, and the
Duplex Mode bit controls switching between full duplex
operation and half duplex operation. The Speed Selection
and Duplex Mode bits have no effect on the mode of oper-
ation when the Auto-Negotiation Enable bit is set.
The Link Speed can be examined through the PHY Status
R
egister (PHYSTS) at address 10h after a Link is
achieved.
The Basic Mode Status Register (BMSR) indicates the set
of
available abilities for technology types, Auto-Negotiation
ability, and Extended Register Capability. These bits are
permanently set to indicate the full functionality of the
DP83848I (only the 100BASE-T4 bit is not set since the
DP83848I does not support that function).
The BMSR also provides status on:
— Whether or not Auto-Negotiation is complete
— Whether or not the Link Partner is advertising that a re-
mote fault has occurred
— Whether or not valid link has been established
— Support for Management Frame Preamble suppression
The Auto-Negotiation Advertisement Register (ANAR)
i
ndicates the Auto-Negotiation abilities to be advertised by
the DP83848I. All available abilities are transmitted by
default, but any ability can be suppressed by writing to the
Table 1. Auto-Negotiation Modes
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Duplex
1 1 0 10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
17 www.national.com
DP83848I
ANAR. Updating the ANAR to suppress an ability is one
way for a management agent to change (restrict) the tech-
nology that is used.
The Auto-Negotiation Link Partner Ability Register
(AN
LPAR) at address 05h is used to receive the base link
code word as well as all next page code words during the
negotiation. Furthermore, the ANLPAR will be updated to
either 0081h or 0021h for parallel detection to either 100
Mb/s or 10 Mb/s respectively.
The Auto-Negotiation Expansion Register (ANER) indi-
cates additional Auto-Negotiation status. The ANER pro-
vides status on:
— Whether or not a Parallel Detect Fault has occurred
— Whether or not the Link Partner supports the Next Page
fu
nction
— Whether or not the DP83848I supports the Next Page
function
— Whether or not the current page being exchanged by
Auto-Negotiation has been received
— Whether or not the Link Partner supports Auto-Negotia-
tion
2.1.3 Auto-Negotiation Parallel Detection
The DP83848I supports the Parallel Detection function as
d
efined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to moni-
tor the receive signal and report link status to the Auto-
N
egotiation function. Auto-Negotiation uses this informa-
tion to configure the correct technology in the event that the
L
ink Partner does not support Auto-Negotiation but is
transmitting link signals that the 100BASE-TX or 10BASE-
T PMAs recognize as valid link signals.
If the DP83848I completes Auto-Negotiation as a result of
Pa
rallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the
Link Partner. Note that bits 4:0 of the ANLPAR will also be
set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may deter-
mine that negotiation completed via Parallel Detection by
re
ading a zero in the Link Partner Auto-Negotiation Able bit
once the Auto-Negotiation Complete bit is set. If configured
for parallel detect mode and any condition other than a sin-
gle good link occurs then the parallel detect fault bit will be
se
t.
2.1.4 Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted
at any time by setting bit 9 (Restart Auto-Negotiation) of the
BMCR to one. If the mode configured by a successful Auto-
Negotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configu-
ration for the link. This function ensures that a valid config-
uration is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a manage-
ment agent, will cause the DP83848I to halt any transmit
da
ta and link pulse activity until the break_link_timer
expires (~1500 ms). Consequently, the Link Partner will go
into link fail and normal Auto-Negotiation resumes. The
DP83848I will resume Auto-Negotiation after the
break_link_timer has expired by issuing FLP (Fast Link
Pulse) bursts.
2.1.5 Enabling Auto-Negotiation via Software
It is important to note that if the DP83848I has been initial-
ized upon power-up as a non-auto-negotiating device
(fo
rced technology), and it is then required that Auto-Nego-
tiation or re-Auto-Negotiation be initiated via software,
bi
t 12 (Auto-Negotiation Enable) of the Basic Mode Control
Reg
ister (BMCR) must first be cleared and then set for any
Auto-Negotiation function to take effect.
2.1.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 seconds to complete. In addition, Auto-Negotiation with
next page should take approximately 2-3 seconds to com-
plete, depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full
de
scription of the individual timers related to Auto-Negotia-
tion.
2.2 Auto-MDIX
When enabled, this function utilizes Auto-Negotiation to
determine the proper configuration for transmission and
reception of data and subsequently selects the appropriate
MDI pair for MDI/MDIX operation. The function uses a ran-
dom seed to control switching of the crossover circuitry.
Th
is implementation complies with the corresponding IEEE
802.3 Auto-Negotiation and Crossover Specifications.
Auto-MDIX is enabled by default and can be configured via
s
trap or via PHYCR (0x19h) register, bits [15:14].
Neither Auto-Negotiation nor Auto-MDIX is required to be
en
abled in forcing crossover of the MDI pairs. Forced
crossover can be achieved through the FORCE_MDIX bit,
bit 14 of PHYCR (0x19h) register.
Note: Auto-MDIX will not work in a forced mode of opera-
tion.
www.national.com 18
DP83848I
2.3 PHY Address
The 5 PHY address inputs pins are shared with the
RXD[3:0] pins and COL pin as shown below.
The DP83848I can be set to respond to any of 32 possible
PH
Y addresses via strap pins. The information is latched
into the PHYCR register (address 19h, bits [4:0]) at device
power-up and hardware reset. The PHY Address pins are
shared with the RXD and COL pins. Each DP83848I or port
sharing an MDIO bus in a system must have a unique
physical address.
The DP83848I supports PHY Address strapping values 0
(
<00000>) through 31 (<11111>). Strapping PHY Address
0 puts the part into Isolate Mode. It should also be noted
that selecting PHY Address 0 via an MDIO write to PHYCR
will not put the device in Isolate Mode. See Section 2.3.1for
more information.
For further detail relating to the latch-in timing requirements
o
f the PHY Address pins, as well as the other hardware
configuration pins, refer to the Reset summary in
Section 6.0.
Since the PHYAD[0] pin has weak internal pull-up resistor
an
d PHYAD[4:1] pins have weak internal pull-down resis-
tors, the default setting for the PHY address is 00001
(0
1h).
Refer to Figure 2 for an example of a PHYAD connection to
external components. In this example, the PHYAD strap-
ping results in address 00011 (03h).
2.3.1 MII Isolate Mode
The DP83848I can be put into MII Isolate mode by writing
t
o bit 10 of the BMCR register or by strapping in Physical
Address 0. It should be noted that selecting Physical
Address 0 via an MDIO write to PHYCR will not put the
device in the MII isolate mode.
When in the MII isolate mode, the DP83848I does not
re
spond to packet data present at TXD[3:0], TX_EN inputs
and presents a high impedance on the TX_CLK, RX_CLK,
RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When
in Isolate mode, the DP83848I will continue to respond to
all management transactions.
While in Isolate mode, the PMD output pair will not transmit
p
acket data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.
The DP83848I can Auto-Negotiate or parallel detect to a
s
pecific technology depending on the receive signal at the
PMD input pair. A valid link can be established for the
receiver even when the DP83848I is in Isolate mode.
Table 2. PHY Address Mapping
Pin # PHYAD Function RXD Function
42 PHYAD0 COL
43 PHYAD1 RXD_0
44 PHYAD2 RXD_1
45 PHYAD3 RXD_2
46 PHYAD4 RXD_3
Figure 2. PHYAD Strapping Example
COL
RXD_0
RXD_1
RXD_2
RXD_3
VCC
2.2kΩ
PHYAD0 = 1
PHYAD1 = 1
PHYAD2 = 0PHYAD3 = 0
PHYAD4= 0
19 www.national.com
DP83848I
2.4 LED Interface
The DP83848I supports three configurable Light Emitting
Diode (LED) pins. The device supports three LED configu-
rations: Link, Speed, Activity and Collision. Function are
multiplexed among the LEDs. The PHY Control Register
(PH
YCR) for the LEDs can also be selected through
address 19h, bits [6:5].
See Table 3 for LED Mode selection.
The LED_LINK pin in Mode 1 indicates the link status of
th
e port. In 100BASE-T mode, link is established as a
result of input receive amplitude compliant with the TP-
PMD specifications which will result in internal generation
of signal detect. A 10 Mb/s Link is established as a result of
the reception of at least seven consecutive normal Link
Pulses or the reception of a valid 10BASE-T packet. This
will cause the assertion of LED_LINK. LED_LINK will deas-
sert in accordance with the Link Loss Timer as specified in
th
e IEEE 802.3 specification.
The LED_LINK pin in Mode 1 will be OFF when no LINK is
p
resent.
The LED_LINK pin in Mode 2 and Mode 3 will be ON to
i
ndicate Link is good and BLINK to indicate activity is
present on either transmit or receive activity.
The LED_SPEED pin indicates 10 or 100 Mb/s data rate of
th
e port. The standard CMOS driver goes high when oper-
ating in 100 Mb/s operation. The functionality of this LED is
i
ndependent of mode selected.
The LED_ACT/COL pin in Mode 1 indicates the presence
o
f either transmit or receive activity. The LED will be ON for
Activity and OFF for No Activity. In Mode 2, this pin indi-
cates the Collision status of the port. The LED will be ON
fo
r Collision and OFF for No Collision.
The LED_ACT/COL pin in Mode 3 indicates the presence
o
f Duplex status for 10 Mb/s or 100 Mb/s operation. The
LED will be ON for Full Duplex and OFF for Half Duplex.
In 10 Mb/s half duplex mode, the collision LED is based on
th
e COL signal.
Since these LED pins are also used as strap options, the
p
olarity of the LED is dependent on whether the pin is
pulled up or down.
2.4.1 LEDs
Since the Auto-Negotiation (AN) strap options share the
L
ED output pins, the external components required for
strapping and LED usage must be considered in order to
avoid contention.
Specifically, when the LED outputs are used to drive LEDs
di
rectly, the active state of each output driver is dependent
on the logic level sampled by the corresponding AN input
upon power-up/reset. For example, if a given AN input is
resistively pulled low then the corresponding output will be
configured as an active high driver. Conversely, if a given
AN input is resistively pulled high, then the corresponding
output will be configured as an active low driver.
Refer to Figure 3 for an example of AN connections to
external components. In this example, the AN strapping
re
sults in Auto-Negotiation with 10/100 Half/Full-Duplex
advertised.
The adaptive nature of the LED outputs helps to simplify
po
tential implementation issues of these dual purpose pins.
Table
3. LED Mode Select
Mode LED_CFG[1]
(bit 6)
LED_CFG[0]
(bit 5)
or (pin40)
LED_LINK LED_SPEED LED_ACT/COL
1 don’t care 1 ON for Good Link
OFF for No Link
ON in 100 Mb/s
OFF in 10 Mb/s
ON for Activity
OFF for No Activity
2 0 0 ON for Good Link
BLINK for Activity
ON in 100 Mb/s
OFF in 10 Mb/s
ON for Collision
OFF for No Collision
3 1 0 ON for Good Link
BLINK for Activity
ON in 100 Mb/s
OFF in 10 Mb/s
ON for Full Duplex
OFF for Half Duplex
LED_LINK
LED_SPEED
LED_ACT/COL
VCC
2.2kΩ
110Ω
110Ω
2.2kΩ
110Ω
AN0 = 1
AN1 = 1
AN_EN = 1
2.2kΩ
Figure 3. AN Strapping and LED Loading Example
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