KAI-16050 16百万像素CCD图像传感器详解

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"KAI−16050 CCD Image Sensor是一份由SemiconductorComponentsIndustries,LLC在2015年发布的技术文档，详细介绍了一款1600万像素的高性能CCD图像传感器。这款传感器采用了TRUESENSE 5.5微米的Interline Transfer CCD平台，具有宽动态范围、卓越的成像性能和灵活的读出架构，支持全分辨率下每秒最多8帧的高速读取。其独特的垂直溢流排水结构有助于抑制图像溢出，并且支持电子快门，提供精确的曝光控制。 TRUESENSE稀疏彩色滤镜阵列的应用，使得该传感器在光敏度上比标准的Bayer滤镜阵列提高了2倍，这对于低光照环境下的拍摄特别有利。这一特性使得KAI-16050在暗光条件下也能捕捉更多细节，提升了影像质量。这款传感器的接口与TRUESENSE 5.5微米Interline Transfer CCD平台的其他设备兼容，这意味着设计一个摄像头时可以方便地支持多个KAI-16050传感器型号，从而节省成本并实现系统的扩展性。表1列出了这款传感器的一些主要规格，包括典型的工作参数，如分辨率（4896x3264像素）、接口配置等。 KAI−16050 CCD Image Sensor是一款针对专业摄影和工业应用的理想选择，它在性能、灵活性和成本效益之间找到了良好的平衡，适合对图像质量和速度有高要求的领域，如机器视觉、无人机摄影或科研设备。"

KAI−16050

www.onsemi.com

PHYSICAL DESCRIPTION

Pin Description and Device Orientation

Figure 5. Package Pin Designations − Top View

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36

72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38

71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37

V3B

Pixel

(1,1)

V3B

V1B

VDDa

VDDb

GND

H2SLa

H2SLb

H1Ba

H1Bb

H2Sa

H2Sb

SUB

N/C

V3T

V1T

VDDc

VDDd

GND

H2SLc

H2SLd

H1Bc

H1Bd

H2Sc

H2Sd

N/C

SUB

V4B

ESD

V4B

V2B

VOUTa

VOUTb

RDa

RDb

OGa

OGb

H2Ba

H2Bb

H1Sa

H1Sb

FDGab

V4T

DevID

V4T

V2T

VOUTc

VOUTd

RDc

RDd

OGc

OGd

H2Bc

H2Bd

H1Sc

H1Sd

FDGcd

ESD

KAI−16050

www.onsemi.com

Table 5. PIN DESCRIPTION

Pin Name Description

1 V3B Vertical CCD Clock, Phase 3, Bottom

3 V1B Vertical CCD Clock, Phase 1, Bottom

4 V4B Vertical CCD Clock, Phase 4, Bottom

5 VDDa Output Amplifier Supply, Quadrant a

6 V2B Vertical CCD Clock, Phase 2, Bottom

7 GND Ground

8 VOUTa Video Output, Quadrant a

9 Ra Reset Gate, Quadrant a

10 RDa Reset Drain, Quadrant a

11 H2SLa Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant a

12 OGa Output Gate, Quadrant a

13 H1Ba Horizontal CCD Clock, Phase 1, Barrier,

Quadrant a

14 H2Ba Horizontal CCD Clock, Phase 2, Barrier,

Quadrant a

15 H2Sa Horizontal CCD Clock, Phase 2,

Storage, Quadrant a

16 H1Sa Horizontal CCD Clock, Phase 1,

Storage, Quadrant a

17 SUB Substrate

18 FDGab Fast Line Dump Gate, Bottom

19 N/C No Connect

20 FDGab Fast Line Dump Gate, Bottom

21 H2Sb Horizontal CCD Clock, Phase 2,

Storage, Quadrant b

22 H1Sb Horizontal CCD Clock, Phase 1,

Storage, Quadrant b

23 H1Bb Horizontal CCD Clock, Phase 1, Barrier,

Quadrant b

24 H2Bb Horizontal CCD Clock, Phase 2, Barrier,

Quadrant b

25 H2SLb Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant b

26 OGb Output Gate, Quadrant b

27 Rb Reset Gate, Quadrant b

28 RDb Reset Drain, Quadrant b

29 GND Ground

30 VOUTb Video Output, Quadrant b

31 VDDb Output Amplifier Supply, Quadrant b

32 V2B Vertical CCD Clock, Phase 2, Bottom

33 V1B Vertical CCD Clock, Phase 1, Bottom

34 V4B Vertical CCD Clock, Phase 4, Bottom

35 V3B Vertical CCD Clock, Phase 3, Bottom

36 ESD ESD Protection Disable

Pin Name Description

72 ESD ESD Protection Disable

71 V3T Vertical CCD Clock, Phase 3, Top

70 V4T Vertical CCD Clock, Phase 4, Top

69 V1T Vertical CCD Clock, Phase 1, Top

68 V2T Vertical CCD Clock, Phase 2, Top

67 VDDc Output Amplifier Supply, Quadrant c

66 VOUTc Video Output, Quadrant c

65 GND Ground

64 RDc Reset Drain, Quadrant c

63 Rc Reset Gate, Quadrant c

62 OGc Output Gate, Quadrant c

61 H2SLc Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant c

60 H2Bc Horizontal CCD Clock, Phase 2, Barrier,

Quadrant c

59 H1Bc Horizontal CCD Clock, Phase 1, Barrier,

Quadrant c

58 H1Sc Horizontal CCD Clock, Phase 1,

Storage, Quadrant c

57 H2Sc Horizontal CCD Clock, Phase 2,

Storage, Quadrant c

56 FDGcd Fast Line Dump Gate, Top

55 N/C No Connect

54 FDGcd Fast Line Dump Gate, Top

53 SUB Substrate

52 H1Sd Horizontal CCD Clock, Phase 1,

Storage, Quadrant d

51 H2Sd Horizontal CCD Clock, Phase 2,

Storage, Quadrant d

50 H2Bd Horizontal CCD Clock, Phase 2, Barrier,

Quadrant d

49 H1Bd Horizontal CCD Clock, Phase 1, Barrier,

Quadrant d

48 OGd Output Gate, Quadrant d

47 H2SLd Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant d

46 RDd Reset Drain, Quadrant d

45 Rd Reset Gate, Quadrant d

44 VOUTd Video Output, Quadrant d

43 GND Ground

42 V2T Vertical CCD Clock, Phase 2, Top

41 VDDd Output Amplifier Supply, Quadrant d

40 V4T Vertical CCD Clock, Phase 4, Top

39 V1T Vertical CCD Clock, Phase 1, Top

38 DevID Device Identification

37 V3T Vertical CCD Clock, Phase 3, Top

1. Liked named pins are internally connected and should have a

common drive signal.

2. N/C pins (19, 55) should be left floating.

剩余32页未读，继续阅读

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