CC3220S/CC3220SF单片无线MCU：安全与低功耗特性详析

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"CC3220S/CC3220SF是TI（Texas Instruments）公司推出的一款SimpleLink™ Wi-Fi单片无线微控制器解决方案，该设备集成了双核架构，包括用户专用的应用微控制器子系统和高度集成的Wi-Fi网络处理器。这些特性使得该芯片在物联网(IoT)安全方面表现出色，支持增强的IoT网络安全、非对称密钥以及独特的设备身份，提供软件IP保护和安全存储功能，确保了设备间的高效且安全通信。该芯片具有先进的低功耗模式，特别适合电池供电应用，内置的电源管理子系统帮助优化能源利用。工作温度范围广泛，支持工业环境，可在-40°C至85°C的严苛条件下稳定运行。此外，CC3220S/CC3220SF通过了Chip-Level Wi-Fi Alliance®的Wi-Fi CERTIFIED™认证，保证了其无线连接性能和合规性。 CC3220S/CC3220SF的核心部分采用ARM Cortex-M4处理器，工作频率高达80MHz，拥有嵌入式内存，包括256KB的随机存取存储器(RAM)，这为其提供了强大的处理能力和足够的数据存储空间。对于应用程序开发者来说，这是一款集成了多种功能的高性能解决方案，可以满足物联网设备的复杂需求，如智能家居、工业自动化和智能穿戴等场景。值得注意的是，在产品文档的最后，有一份重要的通知，涵盖了产品可用性、保修政策、安全关键应用使用注意事项、知识产权声明以及相关的免责声明。在使用前，用户应仔细阅读这些信息，确保理解和遵守相关规定，以充分利用CC3220S/CC3220SF的全部潜力并避免潜在风险。"

CC3220R, CC3220S, CC3220SF

www.ti.com

SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018

Submit Documentation Feedback

Product Folder Links: CC3220R CC3220S CC3220SF

Table 4-2. Pin Attributes (continued)

NO.

SIGNAL NAME

(1)

SIGNAL

TYPE

(2)

PIN MUX

ENCODING

SIGNAL

DIRECTION

PAD STATES

LPDS

(3)

Hib

(4)

nRESET = 0

(5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak

pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.

GPIO15 (PN)

I/O

0 I/O

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

I2C_SDA 5 I/O (open drain)

GSPI_MISO 7 I/O

pDATA9 (CAM_D5) 4 I

GT_CCP06 13 I

SDCARD_DATA0 8 I/O

GPIO16 (PN)

I/O

0 I/O Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

GSPI_MOSI 7 I/O Hi-Z, Pull, Drive

pDATA10 (CAM_D6) 4 I Hi-Z, Pull, Drive

UART1_TX 5 O 1

GT_CCP07 13 I Hi-Z, Pull, Drive

SDCARD_CLK 8 O 0

GPIO17 (PN)

I/O

0 I/O

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

UART1_RX 5 I

GSPI_CS 7 I/O

pDATA11 (CAM_D7) 4 I

SDCARD_CMD 8 I/O

9 VDD_DIG1 (PN) — N/A N/A N/A N/A N/A

10 VIN_IO1 — N/A N/A N/A N/A N/A

11 FLASH_SPI_CLK O N/A O

Hi-Z, Pull,

Drive

(5)

Hi-Z, Pull,

Drive

Hi-Z

12 FLASH_SPI_DOUT O N/A O

Hi-Z, Pull,

Drive

(5)

Hi-Z, Pull,

Drive

Hi-Z

13 FLASH_SPI_DIN I N/A I

Hi-Z, Pull,

Drive

(5)

Hi-Z Hi-Z

14 FLASH_SPI_CS O N/A O 1

Hi-Z, Pull,

Drive

Hi-Z

GPIO22 (PN) I/O 0 I/O

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-ZMcAFSX O 7 O

GT_CCP04 I 5 I

TDI (PN)

I/O

1 I

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

GPIO23 0 I/O

UART1_TX 2 O 1

I2C_SCL 9 I/O (open drain) Hi-Z, Pull, Drive

TDO (PN)

I/O

1 O

Hi-Z, Pull, Drive

Driven high

in SWD;

driven low in

4-wire JTAG

Hi-Z

GPIO24 0 I/O

PWM0 5 O

UART1_RX 2 I

I2C_SDA 9 I/O (open drain)

GT_CCP06 4 I

McAFSX 6 O

18 GPIO28 I/O 0 I/O Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

TCK (PN)

I/O

1 I

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

GT_PWM03 8 O

CC3220R, CC3220S, CC3220SF

SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018

www.ti.com

Submit Documentation Feedback

Product Folder Links: CC3220R CC3220S CC3220SF

Table 4-2. Pin Attributes (continued)

NO.

SIGNAL NAME

(1)

SIGNAL

TYPE

(2)

PIN MUX

ENCODING

SIGNAL

DIRECTION

PAD STATES

LPDS

(3)

Hib

(4)

nRESET = 0

(6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an

output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode

to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

(7) For details on proper use, see Section 4.5.

(8) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode.

For this reason, the pin must be output only when used for digital functions.

(9) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device

between two antennas. These pins must not be used for other functionalities.

TMS (PN)

I/O

I/O Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

GPIO29 0

(6)

GPIO25

0 O Hi-Z, Pull, Drive

Driven low Hi-Z

GT_PWM02 9 O Hi-Z, Pull, Drive

McAFSX 2 O Hi-Z, Pull, Drive

TCXO_EN

N/A

(see

(7)

)

O 0

SOP2 (PN)

N/A

(see

(8)

)

I Hi-Z, Pull, Drive

22 WLAN_XTAL_N —

N/A

(see

(7)

)

N/A N/A N/A N/A

23 WLAN_XTAL_P — N/A N/A N/A N/A N/A

24 VDD_PLL — N/A N/A N/A N/A N/A

25 LDO_IN2 — N/A N/A N/A N/A N/A

26 NC — N/A N/A N/A N/A N/A

27 NC — N/A N/A N/A N/A N/A

28 NC — N/A N/A N/A N/A N/A

(9)

ANTSEL1 O 0 O Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

(9)

ANTSEL2 O 0 O Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

31 RF_BG — N/A N/A N/A N/A N/A

32 nRESET — N/A N/A N/A N/A N/A

33 VDD_PA_IN — N/A N/A N/A N/A N/A

34 SOP1 — N/A N/A N/A N/A N/A

35 SOP0 — N/A N/A N/A N/A N/A

36 LDO_IN1 — N/A N/A N/A N/A N/A

37 VIN_DCDC_ANA — N/A N/A N/A N/A N/A

38 DCDC_ANA_SW — N/A N/A N/A N/A N/A

39 VIN_DCDC_PA — N/A N/A N/A N/A N/A

40 DCDC_PA_SW_P — N/A N/A N/A N/A N/A

41 DCDC_PA_SW_N — N/A N/A N/A N/A N/A

42 DCDC_PA_OUT — N/A N/A N/A N/A N/A

43 DCDC_DIG_SW — N/A N/A N/A N/A N/A

44 VIN_DCDC_DIG — N/A N/A N/A N/A N/A

CC3220R, CC3220S, CC3220SF

www.ti.com

SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018

Submit Documentation Feedback

Product Folder Links: CC3220R CC3220S CC3220SF

Table 4-2. Pin Attributes (continued)

NO.

SIGNAL NAME

(1)

SIGNAL

TYPE

(2)

PIN MUX

ENCODING

SIGNAL

DIRECTION

PAD STATES

LPDS

(3)

Hib

(4)

nRESET = 0

(10) Pin 45 is used by an internal DC/DC (ANA2_DCDC). This pin will be available automatically if serial flash is forced in the CC3220SF

device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.

(11) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level

configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some

applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,

the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to

automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent false

detection, TI recommends using pin 52 for output-only functions.

(10)

GPIO31

I/O

0 I/O

Hi-Z Hi-Z Hi-Z

UART0_RX 9 I

McAFSX 12 O

UART1_RX 2 I

McAXR0 6 I/O

GSPI_CLK 7 I/O

DCDC_ANA2_SW_P

(PN)

—

N/A

(see

(7)

)

N/A N/A N/A N/A

46 DCDC_ANA2_SW_N — N/A N/A N/A N/A N/A

47 VDD_ANA2 — N/A N/A N/A N/A N/A

48 VDD_ANA1 — N/A N/A N/A N/A N/A

49 VDD_RAM — N/A N/A N/A N/A N/A

GPIO0 (PN)

I/O

0 I/O Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

UART0_CTS 12 I Hi-Z, Pull, Drive

McAXR1 6 I/O Hi-Z, Pull, Drive

GT_CCP00 7 I Hi-Z, Pull, Drive

GSPI_CS 9 I/O Hi-Z, Pull, Drive

UART1_RTS 10 O 1

UART0_RTS 3 O 1

McAXR0 4 I/O Hi-Z, Pull, Drive

51 RTC_XTAL_P — N/A N/A N/A N/A N/A

(11)

RTC_XTAL_N (PN)

N/A N/A N/A

Hi-Z, Pull,

Drive

Hi-Z

GPIO32 0 O

Hi-Z, Pull, DriveMcACLK 2 O

McAXR0 4 O

UART0_RTS 6 O 1

GSPI_MOSI 8 O Hi-Z, Pull, Drive

GPIO30 (PN)

I/O

0 I/O Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

UART0_TX 9 O 1

McACLK 2 O

Hi-Z, Pull, Drive

McAFSX 3 O

GT_CCP05 4 I

GSPI_MISO 7 I/O

54 VIN_IO2 — N/A N/A N/A N/A N/A

GPIO1 (PN)

I/O

0 I/O Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

UART0_TX 3 O 1

pCLK (PIXCLK) 4 I Hi-Z, Pull, Drive

UART1_TX 6 O 1

GT_CCP01 7 I Hi-Z, Pull, Drive

56 VDD_DIG2 — N/A N/A N/A N/A N/A

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