DDR4内存标准详述：JEDEC 2GB至16GB规范详解

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"DDR4规范.pdf"文档详细阐述了JEDEC（固态技术协会）制定的DDR4 SDRAM标准，该标准主要针对2GB至16GB容量、x4、x8和x16配置的内存。DDR4是第四代双数据速率同步动态随机存取内存，它相较于前一代产品在性能、功耗和速度方面有显著提升。该标准定义了DDR4 SDRAM的关键特性和功能，包括但不限于时钟频率、数据传输速率、信号完整性、电源管理、工作模式以及电气和热性能参数。它涵盖了内存模块的物理尺寸、引脚布局（ball/signal assignments）以及各种操作条件下的直流（DC）和交流（AC）特性，确保产品的兼容性和互换性。 DDR4标准旨在消除制造商与购买者之间的误解，促进不同厂商生产的产品能在全球范围内实现无缝替换，并帮助消费者在众多选择中快速找到最适合其应用的内存解决方案，无论是国内还是国际市场。JEDEC强调，这些标准的制定并不考虑是否涉及专利、材料或工艺，但明确表示，采用标准并不意味着对专利权的承认或对采用者的责任承担。文档中的“sound approach”可能指的是JEDEC采用了一套全面的方法论来确保标准的质量，包括严谨的审查过程、测试验证以及对最新技术趋势的考量。通过这些规定，DDR4 SDRAM得以达到高性能、高可靠性和低功耗的行业标准，从而推动计算机和电子设备市场的发展。总结来说，"DDR4规范.pdf"文档的核心内容是为DDR4 SDRAM的开发、生产和使用提供了一个统一的技术规范，确保所有符合标准的产品都能满足高性能计算和存储的需求，同时促进了技术进步和市场公平竞争。理解并遵循这些规定对于任何设计或采购DDR4内存的工程师和技术人员都至关重要。

JEDEC Standard No. 79-4

Page 8

3 Functional Description

3.1 Simplified State Diagram

NOTE This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control them. In particular,

situations involving more than on bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail.

Self

Idle

Bank

Precharging

Power

Writing

ACT

ReadA

Read

SRE

REF

PDE

PDX

PDE

Write

ReadA

WriteA

Read

PRE, PREA

Refreshing

Down

Power

Down

Active

ReadA

Reading

WriteA

Active

Precharge

Reading

Writing

Activating

SRX

Read

Write

Calibration

CKE_L

PRE, PREA

Write

WriteA

Initialization

Reset

Procedure

Power

Applied

RESET

from any

state

MPR,

Write

Leveling

MRS

Abbreviation Function Abbreviation Function Abbreviation Function

ACT Activate Read RD,RDS4, RDS8 PDE Enter Power-down

PRE Precharge Read A RDA, RDAS4, RDAS8 PDX Exit Power-down

PREA PRECHARGE All Write WR, WRS4, WRS8 with/without CRC SRE Self-Refresh entry

MRS Mode Register Set Write A WRA,WRAS4, WRAS8 with/without CRC SRX Self-Refresh exit

REF

Refresh, Fine granular-

ity Refresh

RESET_n Start RESET procedure MPR Multi Purpose Register

TEN

Boundary Scan Mode

Enable

MPSM

Vref, DQ training

Boundary

Scan

(X16only)

TEN

RESET

ZQCL

ZQCS,ZQCL

Automatic Sequence

Command Sequence

PDA

IVREFDQ,

MPSM

RTT,Etc

mode

w/ DQ0=Low

MRS

SRX w/

NOP

MRS

SRX w/NOP

w/ Q=Low

JEDEC Standard No. 79-4

Page 9

3.2 Basic Functionality

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4

banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM.

The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with

an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM

consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock

cycle data transfers at the I/O pins.

Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight

or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is

then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE Command are used to select

the bank and row to be activated (BG0-BG1 in x4/8 and BG0 in x16 select the bankgroup; BA0-BA1 select the bank; A0-A17 select

the row; refer to “DDR4 SDRAM Addressing” on Section 2.7 for specific requirements). The address bits registered coincident with

the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge

command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.

Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner.

The following sections provide detailed information covering device reset and initialization, register definition, command descriptions,

and device operation.

3.3 RESET and Initialization Procedure

For power-up and reset initialization, in order to prevent DRAM from functioning improperly default values for the following MR

settings need to be defined.

Gear down mode (MR3 A[3]) : 0 = 1/2 Rate

Per DRAM Addressability (MR3 A[4]) : 0 = Disable

Max Power Saving Mode (MR4 A[1]) : 0 = Disable

CS to Command/Address Latency (MR4 A[8:6]) : 000 = Disable

CA Parity Latency Mode (MR5 A[2:0]) : 000 = Disable

3.3.1 Power-up Initialization Sequence

The following sequence is required for POWER UP and Initialization and is shown in Figure 3.

1. Apply power (RESET_n is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined). RESET_n needs

to be maintained for minimum 200us with stable power. CKE is pulled “ Low” anytime before RESET_n being de-asserted (min.

time 10ns) . The power voltage ramp time between 300mV to V

min must be no greater than 200ms; and during the ramp, V

≥ V

DDQ

and (V

-V

DDQ

) < 0.3volts. VPP must ramp at the same time or earlier than VDD and VPP must be equal to or higher

than VDD at all times.

• V

and V

DDQ

are driven from a single power converter output, AND

• The voltage levels on all pins other than V

DDQ

SSQ

must be less than or equal to V

DDQ

and V

on one side and

must be larger than or equal to V

SSQ

and V

on the other side. In addition, V

is limited to TBDV max once power ramp is

finished, AND

• VrefCA tracks TBD.

• Apply V

without any slope reversal before or at the same time as V

DDQ

• Apply V

DDQ

without any slope reversal before or at the same time as V

& VrefCA.

• Apply VPP without any slope reversal before or at the same time as VDD.

• The voltage levels on all pins other than V

DDQ

SSQ

must be less than or equal to V

DDQ

and V

on one side and

must be larger than or equal to V

SSQ

and V

on the other side.

2. After RESET_n is de-asserted, wait for another 500us until CKE becomes active. During this time, the DRAM will start internal

initialization; this will be done independently of external clocks.

3. Clocks (CK_t,CK_c) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active. Since

CKE is a synchronous signal, the corresponding setup time to clock (tIS) must be met. Also a Deselect command must be

registered (with tIS set up time to clock) at clock edge Td. Once the CKE registered “High” after Reset, CKE needs to be

continuously registered “High” until the initialization sequence is finished, including expiration of tDLLK and tZQinit

4. The DDR4 SDRAM keeps its on-die termination in high-impedance state as long as RESET_n is asserted. Further, the SDRAM

keeps its on-die termination in high impedance state after RESET_n deassertion until CKE is registered HIGH. The ODT input

signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal

may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1 the ODT input signal must be statically held

LOW. In all cases, the ODT input signal remains static until the power up initialization sequence is finished, including the expiration

of tDLLK and tZQinit.

JEDEC Standard No. 79-4

Page 12

3.4 Register Definition

3.4.1 Programming the mode registers

For application flexibility, various functions, features, and modes are programmable in seven Mode Registers, provided by the DDR4

SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. The mode registers are

divided into various fields depending on the functionality and/or modes. As not all the Mode Registers (MR#) have default values

defined, contents of Mode Registers must be initialized and/or re-initialized, i. e. written, after power up and/or reset for proper

operation. Also the contents of the Mode Registers can be altered by re-executing the MRS command during normal operation.

When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within

the accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array

contents, which means these commands can be executed any time after power-up without affecting the array contents. The mode

register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time

required between two MRS commands shown in

Figure 5.

NOTE 1 This timing diagram shows C/A Parity Latency mode is “Disable” case.

NOTE 2 List of MRS commands exception that do not apply to tMRD

- Gear down mode

- C/A Parity Latency mode

- CS to Command/Address Latency mode

- Per DRAM Addressability mode

- VrefDQ training Value, VrefDQ Training mode and VrefDQ training Range

Figure 5 — tMRD Timing

Some of the Mode Register setting affect to address/command/control input functionality. These case, next MRS command can be

allowed when the function updating by current MRS command completed.

This type of MRS command does not apply tMRD timing to next MRS command is listed in Note 2 of Figure 5. These MRS command

input cases have unique MR setting procedure, so refer to individual function description.

The most MRS command to Non-MRS command delay, tMOD, is required for the DRAM to update the features, and is the minimum

time required from an MRS command to a non-MRS command excluding DES shown in

Figure 6.

T0 T1 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2

Tb3

CK_t

CK_c

MRS

tMRD

Command

Valid Valid Valid Valid

Valid ValidValid

Address

CKE

Valid Valid DES

Old Setting Updating Setting

Settings

Tb4

Valid

DES DES DES DES DES

TIME BREAK DON’T CARE

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