Intel
®
82580EB/82580DB GbE Controller — Contents
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8.3.2.9 Extended Interrupt Auto Clear Enable Register (EIAC)....................................................515
8.3.2.10 Extended Interrupt Auto Mask Enable Register (EIAM) ...................................................515
8.3.2.11 GPIE Register ...........................................................................................................515
8.3.3 MSI-X and Vectors .....................................................................................................516
8.3.4 Interrupt Moderation ..................................................................................................517
8.3.5 Clearing Interrupt Causes ...........................................................................................519
8.3.5.1 Auto-Clear ...............................................................................................................519
8.3.5.2 Write to Clear...........................................................................................................519
8.3.5.3 Read to Clear ...........................................................................................................519
8.3.6 Rate Controlled Low Latency Interrupts (LLI).................................................................520
8.3.6.1 Rate Control Mechanism ............................................................................................520
8.3.7 TCP Timer Interrupt ...................................................................................................521
8.3.7.1 Introduction.............................................................................................................521
8.3.7.2 Description ..............................................................................................................521
8.4 802.1q VLAN Support.................................................................................................................521
8.4.1 802.1q VLAN Packet Format ........................................................................................521
8.4.2 802.1q Tagged Frames ...............................................................................................522
8.4.3 Transmitting and Receiving 802.1q Packets ...................................................................522
8.4.3.1 Adding 802.1q Tags on Transmits ...............................................................................522
8.4.3.2 Stripping 802.1q Tags on Receives ..............................................................................523
8.4.4 802.1q VLAN Packet Filtering.......................................................................................523
8.4.5 Double VLAN Support .................................................................................................524
8.4.5.1 Transmit Behavior With External VLAN.........................................................................524
8.4.5.2 Receive Behavior With External VLAN ..........................................................................524
8.5 Configurable LED Outputs ...........................................................................................................525
8.5.1 MODE Encoding for LED Outputs ..................................................................................526
8.6 Memory Error Correction and Detection ........................................................................................526
8.6.1 Management Parity Errors...........................................................................................527
8.7 CPU affinity Features..................................................................................................................528
8.7.1 Direct Cache Access (DCA)..........................................................................................528
8.7.1.1 DCA Description........................................................................................................528
8.7.1.2 Details of Implementation ..........................................................................................529
8.7.2 TLP Process Hints (TPH)..............................................................................................530
8.7.2.1 Steering Tag and Processing Hint Programming ............................................................531
8.8 Virtualization.............................................................................................................................531
8.8.1 Overview ..................................................................................................................531
8.8.1.1 Virtualized System Overview ......................................................................................532
8.8.1.2 VMDq Supported Features..........................................................................................534
8.8.2 Packet Switching (VMDq) Model ...................................................................................535
8.8.2.1 VMDq Assumptions ...................................................................................................535
8.8.2.2 VM Selection ............................................................................................................535
8.8.2.3 L2 Filtering...............................................................................................................535
8.8.2.4 Size Filtering ............................................................................................................535
8.8.2.5 VMDq Receive Packets Switching.................................................................................536
8.8.2.6 Mirroring Support......................................................................................................541
8.8.2.7 VMDq Offload support................................................................................................541
8.8.2.8 Security Features......................................................................................................542
8.8.2.9 External Switch Loopback Support...............................................................................544
8.8.2.10 Switch Control..........................................................................................................544
8.8.3 Virtualization of the Hardware......................................................................................544
8.8.3.1 Per Pool Statistics .....................................................................................................544
8.9 Time SYNC (IEEE1588 and IEEE 802.1AS).....................................................................................545
8.9.1 Overview ..................................................................................................................545
8.9.2 Flow and Hardware/Software Responsibilities.................................................................545
8.9.2.1 TimeSync Indications in Receive and Transmit Packet Descriptors....................................547
8.9.3 Hardware Time Sync Elements.....................................................................................547
8.9.3.1 System Time Structure and Mode of Operation .............................................................548
8.9.3.2 Time Stamp Mechanism .............................................................................................548
8.9.3.3 Time Adjustment Mode of Operation............................................................................550
8.9.4 Time Sync Related Auxiliary Elements...........................................................................550
8.9.4.1 Target Time .............................................................................................................550
8.9.4.2 Configurable Frequency Clock.....................................................................................552
8.9.4.3 Time Stamp Events ...................................................................................................552
8.9.5 Time SYNC Interrupts.................................................................................................552
8.9.6 PTP Packet Structure ..................................................................................................553
8.10 Statistic Counters ......................................................................................................................555
8.10.1 IEEE 802.3 Clause 30 Management ..............................................................................555
8.10.2 OID_GEN_STATISTICS ...............................................................................................556
8.10.3 RMON ......................................................................................................................557
8.10.4 Linux net_device_stats ...............................................................................................557
8.10.5 Statistics Hierarchy. ...................................................................................................558
9.0 PCIe Programming Interface ..................................................................................................561
9.1 PCIe* Compatibility....................................................................................................................561
9.2 Configuration Sharing Among PCI Functions ..................................................................................562
9.3 PCIe Register Map .....................................................................................................................563