LVDS技术详解：高速数据传输的应用与发展

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"LVDS（低电压差分信号）是一种针对现代高性能数据传输应用的新技术。LVDS标准已成为行业中最为流行的差分数据传输标准。" LVDS（Low-Voltage Differential Signaling，低电压差分信号）是National Semiconductor公司提出的一种高速、低功耗、低噪声的数字接口技术。这种信号传输方式在高速数据传输应用中具有显著优势，特别是在半导体、FPGA（现场可编程门阵列）和ASIC（专用集成电路）领域中广泛应用。 LVDS技术的核心在于使用一对差分信号线进行数据传输，通过两个信号之间的电压差来表示信息。相比于单端信号，LVDS能提供更高的数据速率，同时由于采用差分方式，它对电磁干扰（EMI）的抑制能力更强，且具有更低的功耗。LVDS的信号电平通常在几百毫伏范围内，远低于传统的TTL或CMOS信号，因此可以有效减少信号间的串扰，提高系统的可靠性。在实际应用中，LVDS广泛用于显示接口（如LCD显示器）、背板通信、视频传输、网络设备以及嵌入式系统内部的数据传输。例如，LVDS被用作PCIe（ Peripheral Component Interconnect Express）总线的一部分，实现高速数据交换。在FPGA和ASIC设计中，LVDS接口常用来实现高带宽的数据输入输出，确保系统性能。 National Semiconductor作为LVDS技术的先驱，其发布的《LVDS Owner’s Manual》是工程师进行LVDS设计的重要参考资料。手册汇总了LVDS的基础知识和设计概念，旨在帮助工程师节省时间，避免因摸索和试验而带来的成本，从而最大化利用LVDS解决方案的优势。手册的内容可能包括但不限于以下几个方面： 1. LVDS基本原理：解释差分信号的工作机制和LVDS的信号特点。 2. LVDS标准：介绍各种LVDS接口规范，如MIPI D-PHY、LVDS-422、LVDS-485等。 3. 设计指导：提供电路设计、信号路由、噪声管理等方面的实用建议。 4. 兼容性和互操作性：讨论LVDS与其他接口标准的兼容性问题。 5. 电源和接地策略：指导如何有效地供电和接地以优化LVDS系统的性能。 6. 误差检测与纠正：介绍LVDS系统中的错误检测和恢复机制。 7. 实际应用案例：分享成功应用LVDS技术的实例，提供设计灵感。通过深入理解和熟练运用《LVDS Owner’s Manual》，工程师可以更好地掌握LVDS技术，设计出高效、稳定的高速数字系统。

2-3

2.1.3 Maximum switching speed

Maximum switching speed of an LVDS Interface is a complex question, and its answer depends upon several

factors. These factors are the performance of the line driver (edge rate) and receiver, the bandwidth of the

media, and the required signal quality for the application.

Since the driver outputs are very fast, the limitation on speed is commonly restricted by:

1. How fast TTL data can be delivered to the driver – in the case of simple PHY devices that translate a

TTL/CMOS signal to LVDS (i.e. DS90LV047A)

2. Bandwidth performance of the selected media (cable) – type and length dependent

For example, the factor that limits the speed of the DS90LV047A LVDS driver is the rate that TTL data

can be delivered.

National’s Channel Link devices (SerDes) capitalize on the speed mismatch between TTL and LVDS by

serializing the TTL data into a narrower LVDS data stream (more about this later).

2.1.4 Saving power

LVDS technology saves power in several important ways. The power dissipated by the load (the 100W termi-

nation resistor) is a mere 1.2 mW. In comparison, an RS-422 driver typically delivers 3V across a 100W

termination. It dissipates 90 mW of power — 75x more than LVDS.

LVDS devices are implemented in CMOS processes, which provide low static power consumption. The circuit

design of the drivers and receiver require roughly one-tenth the power supply current of PECL/ECL devices.

Aside from the power dissipated in the load and static I

current, LVDS also lowers system power through

its current-mode driver design. This design greatly reduces the frequency component of I

. The I

vs.

frequency plot for LVDS is virtually flat between 10 MHz and 100 MHz. The quad device, DS90C031/2

uses less than 50 mA total, for driver and receiver at 100 MHz. Compare this to TTL/CMOS transceivers

whose dynamic power consumption increases exponentially with frequency.

2.1.5 LVDS configurations

Figure 2.3. Point-to-point configuration

LVDS drivers and receivers are commonly used in a point-to-point configuration, as shown in Figure 2.3.

Dedicated point-to-point links provide the best signal quality due to the clear path they provide. In this

configuration, LVDS is capable of transmitting high-speed signals over substantial lengths of cable while

using remarkably little power and generating very little noise. However, other topologies/configurations are

also possible.

When the system architect is more interested in minimizing the number of interconnects than in raw

performance, LVDS is a great technology to consider. LVDS is well suited to bi-directional signaling and

bus applications.

ReceiverDriver

≈100Ω

LVDS-003

Using LVDS

LVDS.national.com

2-5

5. LVDS transceivers are cost-efficient products that can also be integrated around digital cores providing

a higher level of integration.

6. LVDS moves data much faster than TTL, so multiple TTL signals can be serialized or multiplexed

into a single LVDS channel, reducing board, connectors, and cabling costs.

Figure 2.6. National’s Channel Link chipsets convert a TTL bus into a compact LVDS data stream and back to TTL

In fact, in some applications, the Printed Circuit Board (PCB), cable, and connector cost savings greatly

overshadow any additional silicon costs. Smaller PCBs, cables, and connectors also result in a much more

ergonomic, user-friendly system.

2.3 Embedded LVDS I/O in FPGAs and ASICs

The latest Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs)

are moving into the Bus LVDS application space. These new product offerings have enhanced LVDS drive

characteristics designed to be more compatible with a typical multidrop topology. There are advantages

and disadvantages to these FPGA platforms over discrete solutions. For example, fewer ICs on a PCB

generally lead to simpler designs with fewer interconnects, and integrated solutions are sometimes necessary

when board size is a concern.

System designers should weigh these advantages against the compromises they will be making in signal

integrity. They should also be aware that discrete solutions are typically more cost effective than integrated

FPGA platforms.

Several major design challenges still need to be addressed in order to successfully design a robust backplane

interface.

1. Stub length: This is the trace length from the backplane trace, through the backplane connector to

the Bus LVDS receiver. Long stubs in multidrop and multipoint buses lead to poor signal integrity.

2. ESD protection: Resistance to electrostatic discharge (ESD) improves the reliability of system boards

during insertion and removal events.

3. Capacitiv

e loading:

This is the capacitance seen at the I/O of an activ

e device. H

igh capacitance leads

to low impedance and low noise margin.

TTL

Transmitter Receiver

TTL

4, 5 or 9

channels

21, 28 or 48

channels

plus clock

21, 28 or 48

channels

plus clock

Serializer Deserializer

LVDS

LVDS-008

Using LVDS

LVDS.national.com

2-6

2.3.1 Stub length

Reductions in stub length are one of the best ways to improve the signal integrity of a multidrop or

multipoint bus.

As a rule of thumb, stub lengths should be no longer than 2.5 cm or 1 in., (see Section 5.3.3) It is possible to

design with longer stub trace lengths, but bus noise from signal reflections limit system performance.

A board designer does not always have a great deal of flexibility with respect to the placement of the FPGA

or ASIC on his board. If an LVDS receiver is integrated into a larger IC, its placement depends on a number

of factors. These factors tend to conflict with the signal integrity related needs of the receiver being near

the backplane connector. The designer’s ability to control trace lengths between the connector and the ICs

inputs are further diminished when an FPGA contains a large number of high-speed I/Os.

A discrete solution enables the placement of LVDS I/Os for optimum signal integrity. This is one less factor

that the board designer needs to worry about as the balances the compromises over the placement of the

larger ICs.

2.3.2 ESD protection

Anytime a board or cable is handled or plugged into a system, the opportunity exists for ESD events to

occur. Integrated circuits mounted to the external interfaces on the board are most likely to be in the ESD

event path. Selecting devices with high ESD tolerances will increase the reliability of the board. It is desirable

to isolate and protect sensitive programmable devices from the stresses associated with ESD events with

interface devices from National.

Example HBM ESD protection levels

DS90LV047 >10 kV

DS90LV048 >10 kV

DS90CP22 >5.0 kV

DS92LV090 >4.5 kV

DS92LV040 >4.0 kV

Many of the FPGAs and PLDs pass HBM ESD tests in the range of 1000V to 2000V. For these designs

requiring more protection, a lower-cost, stand-alone LVDS IC provides this protection on behalf of the

high-end ICs.

2.3.3 Capacitive loading

Plug-in cards present capacitive loads on backplane traces. As the loading on the backplane bus traces

increases, their impedance drops. The drop in impedance reduces the available noise margin and the reliability

of operation in the design.

The three factors on a plug-in card that contribute to the capacitive loading on a bus are the:

• Bulk capacitance load resulting from the connector

• PCB trace

• I/O structure of the device

In a good design the connector contributes 2 pF to 3 pF, the trace contributes 2 pF to 3 pF, and the device

contributes 4 pF to 5 pF. The total load in such a design is around 10 pF.

LVDS Owner’s Manual

National Semiconductor’s LVDS Group

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