LMK04816精密时钟调理器：双环PLL低噪声解决方案

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"TI-LMK04816是一款精密时钟调理器，拥有双环PLL（锁相环）架构，适用于对时钟信号质量有严格要求的应用，如FPGA、DAC、ADC和IF系统。该器件具备超低的RMS抖动性能，能有效减少系统中的噪声和抖动，提高系统精度。此外，LMK04816还包含一个集成的低噪声晶体振荡器电路，以及可选择的保持模式和自动/手动触发/恢复功能。其PLL2部分提供标准化1Hz的低噪声基线，并且相位检测器速率高达155MHz。内置的VCO（压控振荡器）频率范围广泛，可在2370MHz至2600MHz之间调整，满足不同应用需求。" LMK04816是德州仪器（TI）推出的一款高性能时钟管理芯片，主要设计用于需要高质量时钟源的系统，如数字信号处理、通信和数据采集系统。这款芯片的两个关键特性是其双环 PLL 架构和低噪声特性。 1. 双环PLL架构：LMK04816包含两个独立的锁相环（PLL），每个都有不同的功能和优化参数。PLL1设计用于提供高稳定性和低噪声的时钟输出，它集成了一个低噪声晶体振荡器电路，确保在输入时钟丢失时能够进入保持模式，维持系统的连续运行。PLL2则具有更高的相位检测器速率，高达155MHz，这使得它可以快速响应频率变化，适应更宽的频率范围。 2. 超低RMS抖动性能：LMK04816提供了极低的均方根（RMS）抖动，100fs RMS在12kHz至20MHz的频段内，123fs RMS在100Hz至20MHz的频段内。这意味着通过LMK04816产生的时钟信号具有极高的稳定性和精度，这对于高分辨率的数字信号处理（如FPGA和DAC）和采样系统（如ADC）至关重要。 3. 输入和输出灵活性：芯片可以接收多种频率的时钟输入（CLKin0, CLKin1, CLKin2），并能够输出多个独立的时钟信号（CLKout0, CLKout1, ..., CLKout9, ...）。这使得LMK04816成为构建复杂时钟树的理想选择，能够为系统中的不同组件提供精确同步的时钟。 4. 自动和手动触发/恢复功能：在某些情况下，如电源故障或系统重启，LMK04816可以自动或手动触发恢复过程，确保时钟信号的连续性和可靠性。 5. 集成的VCO：LMK04816的压控振荡器（VCO）频率范围为2370MHz至2600MHz，可以根据需要进行调整，满足各种系统的需求。VCO的集成减少了外部组件的需求，简化了系统设计。 LMK04816凭借其出色的时钟抖动性能、灵活的输入输出配置以及高级的PLL特性，为高性能系统提供了可靠的时钟解决方案。在需要高精度时钟信号的领域，如无线通信、雷达系统、测试与测量设备以及航空航天应用中，LMK04816都是一个理想的选择。

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8 Detailed Description

8.1 Overview

In default mode of operation, dual PLL mode with internal VCO, the phase frequency detector in PLL1 compares

the active CLKinX reference divided by CLKinX_PreR_DIV and PLL1 R divider with the external VCXO or crystal

attached to the PLL2 OSCin port divided by PLL1 N divider. The external loop filter for PLL1 must be narrow to

provide an ultra clean reference clock from the external VCXO or crystal to the OSCin/OSCin* pins for PLL2.

The phase frequency detector in PLL2 compares the external VCXO or crystal attached to the OCSin port

divided by the PLL2 R divider with the output of the internal VCO divided by the PLL2 N divider and N2 pre-

scaler and optionally the VCO divider. The bandwidth of the external loop filter for PLL2 must be designed to be

wide enough to take advantage of the low in-band phase noise of PLL2 and the low high offset phase noise of

the internal VCO. The VCO output is also placed on the distribution path for the Clock Distribution section. The

clock distribution consists of 6 groups of dividers and delays which drive 12 outputs. Each clock group allows the

user to select a divide value, a digital delay value, and an analog delay. The 6 groups drive programmable output

buffers. Two groups allow their input signal to be from the OSCin port directly.

When a 0-delay mode is used, a clock output is passed through the feedback mux to the PLL1 N Divider for

synchronization and 0-delay.

When an external VCO mode is used, the Fin port is used to input an external VCO signal. PLL2 Phase

comparison is now with this signal divided by the PLL2 N divider and N2 pre-scaler. The VCO divider may not be

used. One less clock input is available when using an external VCO mode.

When a single PLL mode is used, PLL1 is powered down. OSCin is used as a reference to PLL2.

8.1.1 System Architecture

The dual-loop PLL architecture of the LMK04816 provides the lowest jitter performance over the widest range of

output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external

reference clock and uses an external VCXO or tunable crystal to provide a frequency accurate, low phase noise

reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop

bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the

same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated

along its path or from other circuits. This cleaned reference clock provides the reference input to PLL2.

The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (50 kHz to

200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency phase

noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO or

tunable crystal.

Ultralow jitter is achieved by allowing the phase noise of the external VCXO or Crystal to dominate the final

output phase noise at low offset frequencies and phase noise of the internal VCO to dominate the final output

phase noise at high offset frequencies. This results in best overall phase noise and jitter performance.

The LMK04816 allows subsets of the device to be used to increase the flexibility of device. These different

modes are selected using MODE: Device Mode. For instance:

• Dual-Loop Mode - Typical use case of LMK04816. CLKinX used as reference input to PLL1, OSCin port is

connected to VCXO or tunable crystal.

• Single-Loop Mode - Powers down PLL1. OSCin port is used as reference input.

• Clock Distribution Mode - Allows input of CLKin1 to be distributed to output with division, digital delay, and

analog delay.

See Device Functional Modes for more information on these modes.

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Overview (continued)

8.1.2 PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)

The LMK04816 has three reference clock inputs for PLL1, CLKin0, CLKin1, and CLKin2. Ref Mux selects

CLKin0, CLKin1, or CLKin2. Automatic or manual switching occurs between the inputs.

CLKin0, CLKin1, and CLKin2 each have input dividers. The input divider allows different clock input frequencies

to be normalized so that the frequency input to the PLL1 R divider remains constant during automatic switching.

By programming these dividers such that the frequency presented to the input of the PLL1_R divider is the same

prevents the user from needing to reprogram the PLL1 R divider when the input reference is changed to another

CLKin port with a different frequency.

CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin).

Fast manual switching between reference clocks is possible with a external pins Status_CLKin0, Status_CLKin1,

Status_CLKin2.

8.1.3 PLL1 Tunable Crystal Support

The LMK04816 integrates a crystal oscillator on PLL1 for use with an external crystal and varactor diode to

perform jitter cleaning.

The LMK04816 must be programmed to enable Crystal mode.

8.1.4 VCXO and CRYSTAL-Buffered Outputs

The LMK04816 provides a dedicated output which is a buffered copy of the PLL2 reference input. This reference

input is typically a low-noise VCXO or Crystal. When using a VCXO, this output can be used to clock external

devices such as microcontrollers, FPGAs, CPLDs, and so forth. before the LMK04816 is programmed.

The OSCout0 buffer output type is programmable to LVDS, LVPECL, or LVCMOS.

The dedicated output buffer OSCout0 can output frequency lower than the VCXO or Crystal frequency by

programming the OSC Divider. The OSC Divider value range is 1 to 8. Each OSCoutX can individually choose to

use the OSC Divider output or to bypass the OSC divider.

Two clock output groups can also be programmed to be driven by OSCin. This allows a total of 4 additional

differential outputs to be buffered outputs of OSCin. When programmed in this way, a total of 6 differential

outputs can be driven by a buffered copy of OSCin.

VCXO and Crystal-buffered outputs cannot be synchronized to the VCO clock distribution outputs. The assertion

of SYNC still causes these outputs to become low. Because these outputs turn off and on asynchronously with

respect to the VCO sourced clock outputs during a SYNC, it is possible for glitches to occur on the buffered clock

outputs when SYNC is asserted and unasserted. If the NO_SYNC_CLKoutX_Y bits are set these outputs are not

affected by the SYNC event except that the phase relationship changes with the other synchronized clocks

unless a buffered clock output is used as a qualification clock during SYNC.

8.1.5 Frequency Holdover

The LMK04816 supports holdover operation to keep the clock outputs on frequency with minimum drift when the

reference is lost until a valid reference clock signal is re-established.

8.1.6 Integrated Loop Filter Poles

The LMK04816 features programmable 3rd and 4th order loop filter poles for PLL2. These internal resistors and

capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th order loop filter

response. The integrated programmable resistors and capacitors compliment external components mounted near

the chip.

These integrated components can be effectively disabled by programming the integrated resistors and capacitors

to their minimum values.

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Overview (continued)

8.1.7 Internal VCO

The output of the internal VCO is routed to a mux which allows the user to select either the direct VCO output or

a divided version of the VCO for the clock distribution path. This same selection is also fed back to the PLL2

phase detector through a prescaler and N-divider.

The mux selectable VCO divider has a divide range of 2 to 8 with 50% output duty cycle for both even and odd

divide values.

The primary use of the VCO divider is to achieve divides greater than the clock output divider supports alone.

8.1.8 External VCO Mode

The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04816.

Using an external VCO reduces the number of available clock inputs by one.

8.1.9 Clock Distribution

The LMK04816 features a total of 12 outputs driven from the internal or external VCO.

All VCO driven outputs have programmable output types. They can be programmed to LVPECL, LVDS, or

LVCMOS. When all distribution outputs are configured for LVCMOS or single ended LVPECL a total of 24

outputs are available.

If the buffered OSCin output OSCout0 is included in the total number of clock outputs the LMK04816 is able to

distribute, then up to 13 differential clocks or up to 26 single-ended clocks may be generated with the LMK04816.

The following sections discuss specific features of the clock distribution channels that allow the user to control

various aspects of the output clocks.

8.1.9.1 CLKout Divider

Each clock group, which is a pair of outputs such as CLKout0 and CLKout1, has a single clock output divider.

The divider supports a divide range of 1 to 1045 (even and odd) with 50% output duty cycle. When divides of 26

or greater are used, the divider an delay block uses extended mode.

The VCO Divider may be used to reduce the divide needed by the clock group divider so that it may operate in

normal mode instead of extended mode. This can result in a small current saving if enabling the VCO divider

allows 3 or more clock output divides to change from extended to normal mode.

8.1.9.2 CLKout Delay

The clock distribution section includes both a fine (analog) and coarse (digital) delay for phase adjustment of the

clock outputs.

The fine (analog) delay allows a nominal 25-ps step size and range from 0 to 475 ps of total delay. Enabling the

analog delay adds a nominal 500 ps of delay in addition to the programmed value. When adjusting analog delay,

glitches may occur on the clock outputs being adjusted. Analog delay may not operate at frequencies above the

minimum-ensured maximum output frequency of 1536 MHz.

The coarse (digital) delay allows a group of outputs to be delayed by 4.5 to 12 clock distribution path cycles in

normal mode, or from 12.5 to 522 VCO cycles in extended mode. The delay step can be as small as half the

period of the clock distribution path by using the CLKoutX_Y_HS bit provided the output divide value is greater

than 1. For example, 2-GHz VCO frequency without using the VCO divider results in 250-ps coarse tuning steps.

The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.

There are 3 different ways to use the digital (coarse) delay.

1. Fixed Digital Delay

2. Absolute Dynamic Digital Delay

3. Relative Dynamic Digital Delay

These are further discussed in the Device Functional Modes.

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Overview (continued)

8.1.9.3 Programmable Output Type

For increased flexibility all LMK04816 clock outputs (CLKoutX) and OSCout0 can be programmed to an LVDS,

LVPECL, or LVCMOS output type.

Any LVPECL output type can be programmed to 700, 1200, 1600, or 2000-mVpp amplitude levels. The 2000-

mVpp LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp

differential swing for compatibility with many data converters and is also known as 2VPECL.

8.1.9.4 Clock Output Synchronization

Using the SYNC input causes all active clock outputs to share a rising edge. See Clock Output Synchronization

(SYNC) for more information.

The SYNC event also causes the digital delay values to take effect.

8.1.10 0-Delay

The 0-delay mode synchronizes the input clock phase to the output clock phase. The 0-delay feedback may

performed with an internal feedback loop from any of the clock groups or with an external feedback loop into the

FBCLKin port as selected by the FEEDBACK_MUX.

Without using 0-delay mode, there are n possible fixed phase relationships from clock input to clock output

depending on the clock output divide value.

Using an external 0-delay feedback reduces the number of available clock inputs by one.

8.1.11 Default Start-Up Clocks

Before the LMK04816 is programmed, CLKout8 is enabled and operating at a nominal frequency and CLKout6

and OSCout0 are enabled and operating at the OSCin frequency. These clocks can be used to clock external

devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04816 is programmed.

For CLKout6 and OSCout0 to work before the LMK04816 is programmed the device must not be using Crystal

mode.

8.1.12 Status Pins

The LMK04816 provides status pins which can be monitored for feedback or in some cases used for input

depending upon device programming. For example:

• The Status_Holdover pin may indicate if the device is in holdover mode.

• The Status_CLKin0 pin may indicate the LOS (loss-of-signal) for CLKin0.

• The Status_CLKin0 pin may be an input for selecting the active clock input.

• The Status_LD pin may indicate if the device is locked.

The status pins can be programmed to a variety of other outputs including analog lock detect, PLL divider

outputs, combined PLL lock detect signals, PLL1 Vtune railing, readback, etc. Refer to the MICROWIRE

programming section of this datasheet for more information. Default pin programming is captured in Table 17.

8.1.13 Register Readback

Programmed registers may be read back using the MICROWIRE interface. For readback one of the status pins

must be programmed for readback mode.

At no time may registers be programed to values other than the valid states defined in the datasheet.

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