AN625
20 Rev. 0.1
4 = CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g. TX Direct Mode Data In).
The actual function of this pin is controlled by other properties.
5 = 32 kHz clock. Outputs 32 kHz clock selected using GLOBAL_CLK_CFG:CLK_32K_SEL. Output low if the
32 kHz clock is not enabled.
6 = BOOT_CLK. Outputs boot clock. This will only output when the device is in SPI ACTIVE state because that is the
only time the boot clock is active.
7 = Divided MCU clock. Outputs divided clock. Output divided boot clock in SPI ACTIVE state, Output low while in
SLEEP state as the divided clock source is not running, and Output divided XTAL in all other states. The divider
is configured using GLOBAL_CLK_CFG:DIVIDED_CLK_SEL
8 = CTS. Output High when clear to send a new command, output low otherwise.
9 = INV_CTS. Output low when clear to send a new command, output high otherwise.
10 = Output low unless command overlap occurs. When command overlap occurs output goes high until the rising
edge of CTS.
11 = SPI. Serial data out.
12 = Output low until power on reset is complete then output high.
13 = Output low normally. Pulses high when calibration timer expires. To use the calibration timer, the 32 kHz clock
must be enabled. Calibration timer period is configured using GLOBAL_WUT_CONFIG:WUT_CAL_PERIOD
and enabled by GLOBAL_WUT_CONFIG:CAL_EN.
14 = Output low normally. Pulses high when wakeup timer expires. To use the wakeup timer the 32 kHz clock must
be enabled. The wut period is configured using GLOBAL_WUT_M_15_8, GLOBAL_WUT_M_7_0 and
GLOBAL_WUT_R and enabled by GLOBAL_WUT_CONFIG:WUT_EN.
15 = unused0
16 = TX data CLK output to be used in conjuction with TX Data pin.
17 = RX data CLK output to be used in conjuction with RX Data pin.
18 = unused1
19 = TX data. This option is not to be used for Tx direct mode input. For Tx direct mode input, use option 4.
20 = RX data.
21 = RX raw data.
22 = Antenna 1 Switch used for antenna diversity.
23 = Antenna 2 Switch used for antenna diversity.
24 = High when a valid preamble is detected. Returns to output low after a packet is received or sync word timeout
occurs.
25 = High when an invalid preamble is detected. Output low normally. Pulses output high when the preamble is not
detected within a period of time (determined by PREAMBLE_CONFIG_STD_2:RX_PREAMBLE_TIMEOUT)
after the demodulator is enabled.
26 = High when a sync word is detected. Returns to output low after the packet is received.
27 = High when RSSI above clear channel assesment threshold, low when below threshold. Threshold set by
MODEM_RSSI_THRESH.
32 = High while in the transmit state.
33 = High while in the receive state.
34 = High while the rx fifo is almost full.
35 = High while the tx fifo is almost empty.
36 = High while the battery voltage is low.
37 = High when RSSI above clear channel assesment threshold. Goes low on sync detect or exiting rx state.
38 = Toggles when hop occurs.
39 = Toggles when the hop table wraps.
NIRQ_DRV_PULL
0 = Disable pullup. Recommended setting if pin is driven.
1 = Enable pullup.
NIRQ_MODE[5:0]
0 = Do not modify the behavior of this pin.
1 = Input and output drivers disabled.