ARM Developer Suite 1.2: Assembler Guide

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"ADS_ARM_Assembler_Guide" 本文档是ARMLimited发布的《ARM Developer Suite Version 1.2 Assembler Guide》的版本信息和版权声明。该指南详细介绍了如何使用ADS（ARM Developer Suite）中的汇编器工具，这是一套用于开发基于ARM架构的嵌入式系统的集成开发环境。在ARM Developer Suite 1.2版本中，汇编器是用于将程序员编写的汇编语言代码转换成机器可执行的二进制代码的关键组件。ADS提供了一种高效且功能强大的方式来编写针对ARM处理器的低级代码，这对于优化性能和理解硬件工作原理至关重要。在文档的"Release Information"部分，我们了解到此指南可能已经历了多次更新和改进，以适应产品的不断发展和增强。然而，任何信息或产品描述都不能未经版权所有者事先书面许可而被改编或复制。同时，ARM明确声明，尽管他们以良好的信念提供所有产品和使用细节，但对产品及其用途的任何明示或暗示的保证，包括但不限于适销性和特定目的适用性的保证，均予以排除。 ADS汇编器支持ARM架构的汇编指令集，这包括一系列数据处理、分支、浮点运算以及向量运算等指令。开发者可以利用这些指令来实现高效的算法和低级别的系统控制。此外，该工具还可能提供了宏定义、伪指令和其他高级特性，以帮助简化代码编写和提高代码复用性。在实际应用中，汇编语言通常用于编写操作系统内核、设备驱动程序、实时操作系统（RTOS）以及对性能有严格要求的软件模块。通过掌握ADS汇编器，开发者能够深入理解ARM处理器的工作机制，并能针对性地优化代码，提升软件在ARM平台上的运行效率。该文档可能包含了汇编语言的基本语法、指令集的详细说明、汇编器选项、链接器脚本、错误处理和调试技巧等内容，为开发者提供全面的参考和支持。对于那些需要在ARM平台上进行底层编程的工程师来说，这是一份极其重要的参考资料。

Writing ARM and Thumb Assembly Language

2.2.3 Processor mode

ARM processors support up to seven processor modes, depending on the architecture

version. These are:

• User

• FIQ - Fast Interrupt Request

• IRQ - Interrupt Request

• Supervisor

• Abort

• Undefined

• System (ARM architecture v4 and above).

All modes except User mode are referred to as privileged modes.

Applications that require task protection usually execute in User mode. Some

embedded applications might run entirely in Supervisor or System modes.

Modes other than User mode are entered to service exceptions, or to access privileged

resources. Refer to the Handling Processor Exceptions chapter in ADS Developer

Guide, and ARM Architecture Reference Manual for more information.

2.2.4 Registers

ARM processors have 37 registers. The registers are arranged in partially overlapping

banks. There is a different register bank for each processor mode. The banked registers

give rapid context switching for dealing with processor exceptions and privileged

operations. Refer to ARM Architecture Reference Manual for a detailed description of

how registers are banked.

The following registers are available in ARM architecture v3 and above:

• 30 general-purpose, 32-bit registers

• The program counter (pc) on page 2-5

• The Current Program Status Register (CPSR) on page 2-5

• Five Saved Program Status Registers (SPSRs) on page 2-5.

30 general-purpose, 32-bit registers

Fifteen general-purpose registers are visible at any one time, depending on the current

processor mode, as r0, r1, ... ,r13, r14.

By convention, r13 is used as a stack pointer (sp) in ARM assembly language. The C

and C++ compilers always use r13 as the stack pointer.

Writing ARM and Thumb Assembly Language

In User mode, r14 is used as a link register (lr) to store the return address when a

subroutine call is made. It can also be used as a general-purpose register if the return

address is stored on the stack.

In the exception handling modes, r14 holds the return address for the exception, or a

subroutine return address if subroutine calls are executed within an exception. r14 can

be used as a general-purpose register if the return address is stored on the stack.

The program counter (pc)

The program counter is accessed as r15 (or pc). It is incremented by one word (four

bytes) for each instruction in ARM state, or by two bytes in Thumb state. Branch

instructions load the destination address into the program counter. You can also load the

program counter directly using data operation instructions. For example, to return from

a subroutine, you can copy the link register into the program counter using:

MOV pc,lr

During execution, r15 does not contain the address of the currently executing

instruction. The address of the currently executing instruction is typically pc–8 for

ARM, or pc–4 for Thumb.

The Current Program Status Register (CPSR)

The CPSR holds:

• copies of the Arithmetic Logic Unit (ALU) status flags

• the current processor mode

• interrupt disable flags.

The ALU status flags in the CPSR are used to determine whether conditional

instructions are executed or not. Refer to Conditional execution on page 2-20 for more

information.

On Thumb-capable processors, the CPSR also holds the current processor state (ARM

or Thumb).

On ARM architecture v5TE, the CPSR also holds the Q flag (see The ALU status flags

on page 2-20).

Five Saved Program Status Registers (SPSRs)

The SPSRs are used to store the CPSR when an exception is taken. One SPSR is

accessible in each of the exception-handling modes. User mode and System mode do

not have an SPSR because they are not exception handling modes. Refer to the

Handling Processor Exceptions chapter in ADS Developer Guide for more information.

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