VHDL实现m序列生成器

signal fdbk       : std_logic;          --LFSR的反馈信号
  signal shift_out  : std_logic_vector(8 downto 0):="111111111";    --LFSR
process(clk) 
  begin
    if(clk'event and clk='0') then                      --当50Hz电压或电流信号方波的下降沿到来时
           if reset='0' then                                     --如果P16=0为M序列控制
     shift_out(8 downto 1) <= shift_out(7 downto 0);  --第0到第7位分别传递给高位
                   shift_out(0) <= fdbk;                            --反馈信号传递给第0位
   m<= shift_out(8);                           --第8位作为控制信号输出，n=9，长度为511的m序列


-repick

process (clk)
 begin
  fdbk <= shift_out(tap1) xor shift_out(tap2);
   if (clk'event and clk='1')  then
       if (reset = '0') then
          shift_out <= (others => '1');                             ------初始状态全1
       else 
          shift_out(length1 downto 1) <= shift_out(length1-1 downto 0);           
          shift_out(0) <= fdbk;
end if;
   end if;
end process;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fp is
    Port ( clkin : in  STD_LOGIC;
        clkout : inout  STD_LOGIC;
           led : out  STD_LOGIC);
end fp;

architecture Behavioral of fp is
signal count : std_logic_vector (24 downto 0);
begin
process(clkin)
begin
if(clkin'event and clkin='1')then