TLV320AIC3XXX系列音频编解码器技术规格

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"此资源是TI公司的TLV320AIC3XXX系列音频编解码器的数据表，主要涵盖TLV320AIC3111型号。该器件适用于便携式音频设备、移动互联网设备以及有源滤波应用等。" TLV320AIC3111是一款由德州仪器（TI）推出的低功耗、高性能音频编解码器，设计用于提供立体声音频数模转换器(DAC)和单声道模拟数模转换器(ADC)功能。该器件的主要特点包括： 1. **高音质**：立体声DAC拥有95dB的信噪比(SNR)，确保了高质量的音频输出；单声道ADC则具有91dB的SNR，保证了录音的清晰度。 2. **宽范围采样率支持**：支持从8kHz到192kHz的独立DAC和ADC采样率，适应多种音频应用场景。 3. **嵌入式miniDSP**：内置指令可编程的miniDSP，允许用户自定义滤波器设置，如用户可编程的双极点滤波器(biquad)和有限冲击响应(FIR)滤波器，用于数字音频处理。 4. **立体声Class-D扬声器放大器**：集成了一个1.29W的立体声Class-D BTL 8-Ω扬声器驱动器，可以直接连接电池，降低了系统的复杂性。 5. **多种输入接口**：提供一个差分和三个单端输入，带有混音和电平控制功能，增加了设计的灵活性。 6. **麦克风功能**：包括带偏置、前级增益放大器(PGA)和自动增益控制(AGC)的麦克风输入，优化了音频输入质量。 7. **数字混合能力**：支持数字混合功能，使得音频处理更加多样和高效。 8. **高集成度**：将音频编码和解码、放大器、滤波器等多个功能集成在一个芯片上，大大减少了外部组件的需求，降低了系统成本和板级空间。这款芯片广泛应用于各种便携式音频设备，如MP3播放器、智能手机和平板电脑，以及移动互联网设备，同时还适用于需要高级音频处理和滤波功能的适应性过滤应用。其低功耗特性使其在电池供电的设备中尤为适用，能够延长设备的运行时间。TLV320AIC3111是一款高度灵活且功能强大的音频解决方案，适合对音频性能和电源效率有较高要求的设计。

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0 5 10 15 20

Amplitude − dBFS

G023

AVDD = HPVDD = 3.3 V

IOVDD = SPLVDD = 3.3 V

DVDD = 1.8 V

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0 5 10 15 20

Amplitude − dBFS

G026

AVDD = HPVDD = 3.3 V

IOVDD = SPLVDD = 3.3 V

DVDD = 1.8 V

Channel Gain − dB

100

−10 0 10 20 30 40 50 60 70 80

SNR − dB

G022

Diff = 10k

Diff = 20k

Diff = 40k

SE = 40k

SE = 20k

SE = 10k

f − Frequency − kHz

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0 50 100 150 200

Amplitude − dBFS

G028

AVDD = HPVDD = 3.3 V

IOVDD = SPLVDD = 3.3 V

DVDD = 1.8 V

TLV320AIC3111

SLAS644D –JULY 2009–REVISED MAY 2012

www.ti.com

AMPLITUDE SNR

vs vs

FREQUENCY PGA CHANNEL GAIN

Figure 4-5. Frequency Response, Audio ADC Channel Figure 4-6.

4.2 DAC Performance

AMPLITUDE AMPLITUDE

vs vs

FREQUENCY FREQUENCY

Figure 4-7. FFT – DAC to Line Output Figure 4-8. FFT – DAC to Headphone Output

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Product Folder Link(s) :TLV320AIC3111

TLV320AIC3111

SLAS644D –JULY 2009–REVISED MAY 2012

www.ti.com

• AGC and DRC

• Two miniDSP digital signal-processing blocks (record and playback paths)

• Beep generator

• Stereo headphone/lineout amplifier

• Class-D stereo amplifier for 8-Ω speakers

• Pin-controlled or register-controlled volume level

• Power-down de-pop and power-up soft start

• Analog inputs

• I

C control interface

• Power-down control block

Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I

interface is used to write to the control registers to configure the device.

The I

C address assigned to the TLV320AIC3111 is 001 1000. This device always operates in an I

slave mode. All registers are 8-bit, and all writable registers have read-back capability. The device auto-

increments to support sequential addressing and can be used with I

C fast mode. Once the device is

reset, all appropriate registers are updated by the host processor to configure the device as needed by the

user.

5.2.1 Device Initialization

5.2.1.1 Reset

The TLV320AIC3111 internal logic must be initialized to a known condition for proper device function. To

initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low

for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up.

It is recommended that while the DVDD supply is being powered up, the RESET pin be pulled low.

The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the

device.

5.2.1.2 Device Start-Up Lockout Times

After the TLV320AIC3111 is initialized through hardware reset at power up or software reset, the internal

memories are initialized to default values. This initialization takes place within 1 ms after pulling the

RESET signal high. During this initialization phase, no register-read or register-write operation should be

performed on ADC or DAC coefficient buffers. Also, no block within the codec should be powered up

during the initialization phase.

5.2.1.3 PLL Start-Up

Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up

command of the PLL and before the clocks are available to the codec. This delay is to ensure stable

operation of the PLL and clock-divider logic.

5.2.1.4 Power-Stage Reset

The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has

occurred. Using this reset re-enables the output stage without resetting all of the registers in the device.

Each of the four power stages has its own dedicated reset bit. The headphone power-stage reset is

performed by setting page 1 / register 31, bit D7 for HPL and by setting page 1 / register 31, bit D6 for

HPR. The speaker power-stage reset is performed by setting page 1 / register 32, bit D7 for SPLP and

SPLM, and by setting page 1 / register 32, bit D6 for SPRP and SPRM.

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Product Folder Link(s) :TLV320AIC3111

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