STM32L432K：超低功耗Cortex-M43微控制器详细数据手册

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Functional overview STM32L432KB STM3L432KC

16/149 DocID028798 Rev 2

3.7 Boot modes

At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select

one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the

value of a user option bit to free the GPIO pad if needed.

A Flash empty check mechanism is implemented to force the boot from system flash if the

first flash memory location is not programmed and if the boot selection is configured to boot

from main flash.

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART, I2C, SPI and USB FS in Device mode through DFU (device firmware

upgrade).

3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.9 Power supply management

3.9.1 Power supply schemes

• V

= 1.71 to 3.6 V: external power supply for I/Os (V

DDIO1

), the internal regulator and

the system analog such as reset, power management and internal clocks. It is provided

externally through V

pins.

• V

DDA

= 1.62 V (ADCs/COMPs) / 1.8 (DACs/OPAMP) to 3.6 V: external analog power

supply for ADCs, DACs, OPAMP, Comparators and Voltage reference buffer. The V

DDA

voltage level is independent from the V

voltage.

Note: When the functions supplied by V

DDA

or V

DDUSB

are not used, these supplies should

preferably be shorted to V

Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V

tolerant (refer to

Table 17: Voltage characteristics).

Note: V

DDIOx

is the I/Os general purpose digital functions supply. V

DDIOx

represents V

DDIO1

, with

DDIO1

= V

Functional overview STM32L432KB STM3L432KC

18/149 DocID028798 Rev 2

3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main

regulator (MR) and the low-power regulator (LPR).

• The MR is used in the Run and Sleep modes and in the Stop 0 mode.

• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is

also used to supply the 16 Kbyte SRAM2 in Standby with RAM2 retention.

• Both regulators are in power-down in Standby and Shutdown modes: the regulator

output is in high impedance, and the kernel circuitry is powered down thus inducing

zero consumption.

The ultralow-power STM32L432xx supports dynamic voltage scaling to optimize its power

consumption in run mode. The voltage from the Main Regulator that supplies the logic

(VCORE) can be adjusted according to the system’s maximum operating frequency.

There are two power consumption ranges:

• Range 1 with the CPU running at up to 80 MHz.

• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also

limited to 26 MHz.

The VCORE can be supplied by the low-power regulator, the main regulator being switched

off. The system is then in Low-power run mode.

• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with

independent clock can be clocked by HSI16.

3.9.4 Low-power modes

The ultra-low-power STM32L432xx supports seven low-power modes to achieve the best

compromise between low-power consumption, short startup time, available peripherals and

available wakeup sources:

By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the

user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with VCORE supplied by the low-power regulator to minimize

the regulator's operating current. The code can be executed from SRAM or from Flash,

DocID028798 Rev 2 19/149

STM32L432KB STM3L432KC Functional overview

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the low-

power run mode.

• Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI

RC and the HSI16 RC are disabled. The LSE or LSI is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode

to detect their wakeup condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,

most of the VCORE domain is put in a lower leakage mode.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller

wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator

remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI

up to 48 MHz or HSI16, depending on software configuration.

• Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The

internal regulator is switched off so that the VCORE domain is powered off. The PLL,

the MSI RC and the HSI16 RC are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with

internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1 and register contents are lost except for registers

in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in

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