NVIDIA Jetson TX2 OEM设计指南：优化接口与性能

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本指南深入探讨了NVIDIA Jetson TX2系统模块(SOM)的OEM产品设计，特别是针对硬件接口优化的一些建议和指导。TX2基于Parker系列SoC的Tegra X2芯片，旨在帮助工程师们充分利用TX2的强大性能。以下是该文档中的关键知识点： 1. **硬件平台概述**: - Jetson TX2是专为工业级应用设计的嵌入式系统，集成了高性能计算能力和深度学习加速器。 - SoC架构使得TX2能够处理复杂的任务，包括视觉处理、机器学习和物联网(IoT)应用。 2. **电源管理**: - 提供了关于CARRIER_PWR_ON引脚的拉高建议，并更新了有关RESET_OUT#、SLEEP#的电源系统引脚描述。 - 新增了Power Block图，显示了CARRIER_PWR_ON、POWER_BTN#和SLEEP#上的拉高，以及充电器存在的自动上电机制。 - 添加了Deep Sleep (SC7) 工作模式，有利于延长电池续航或降低功耗。 3. **USB 3.0接口**: - 文档中包含了USB 3.0的电气规格，确保了高速数据传输的兼容性和稳定性。 - 更新了阻抗规范和非交错TX/RX线对的间距建议，提高信号质量。 4. **PCIe接口**: - 删除了关于最大跟踪长度的路由指南，因为这是针对下拉设计的，与TX2的使用场景有所不同，可能需要根据实际应用调整。 5. **文档版本历史**: - 初始发布于2017年5月，随后在同年9月更新，增加了更多关于电源、USB 3.0和PCIe接口的技术细节。通过阅读这份OEM产品设计指南，工程师们可以了解如何将TX2的硬件特性整合到他们的产品中，以实现最佳性能和系统兼容性。在进行设计时，需关注电源管理、接口标准的正确实施以及针对特定功能的优化策略，以确保产品的高效运行和用户友好。同时，随着技术的不断演进，持续关注文档的更新以保持设计的与时俱进是至关重要的。

NVIDIA Jetson TX2 OEM Product Design Guide

JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 16

Figure 11. Deep Sleep (SC7) Entry/Exit Sequence

CARRIER_PWR_ON

VIN_PWR_BAD#

VDD_IN

RESET_OUT#

SC7 Entry SC7 Exit

CARRIER_STBY#

(Tegra X2 SOC_PWR_REQ)

VDD_3V3_SLP

VDD_5V0_SLP

VDD_12V_SLP

VDD_5V0_HDMI_CON

SC7 Entry/Exit Trigger

Carrier Board VDD_1V8

3.7 Optional Auto-Power-On Support

Jetson TX2 includes circuitry on the module to support Auto-Power-On. This allows the platform to power on when VDD_IN is

first powered, instead of waiting for a power button press. In order to enable this feature, the CHARGER_PRSNT# pin should

be tied to GND.

This section provides guidance for modifying a carrier board design to power the platform on when VDD_IN is first powered,

instead of waiting for a power button press. In order to power the system on without a power button, a specific sequence is

required between the time the VDD_IN power (5.5V-19.6V) is connected and the CHARGER_PRSNT# pin on Jetson TX2 is

driven low. The CHARGER_PRSNT# pin connects to the Jetson TX2 PMIC and requires a minimum delay of 300ms from the

point VDD_IN reaches its minimum level (5.5V) before it can be driven low. Four options to meet this requirement and allow

Auto-Power-On are described:

▪ Built-in Auto-Power-On circuit: Not available on Jetson TX1.

▪ Microcontroller: Recommended if a microcontroller is already being used to control power-on.

▪ Supervisor IC: Using a supervisor IC and related discrete devices to meet the sequencing requirements.

▪ Discrete Circuit: Circuit using only discrete devices to meet the sequencing requirements

Built-in Auto-Power-On circuit

Jetson TX2 includes circuitry on the module to support Auto-Power-On. In order to enable this feature, the

CHARGER_PRSNT# pin should be tied to GND. This option is not compatible with Jetson TX1 which does not have this

circuitry.

Microcontroller

If a microcontroller is already present on the carrier board and is used to power the system on when the main power source is

connected, then it can be used to support Auto-Power-On with the following conditions:

▪ After the microcontroller is out of reset wait 300ms before driving CHARGER_PRSNT# low or pulsing

POWER_BTN# low

▪ If the POWER_BTN# pin is used, it should be held low for a time period between 50ms & 5sec.

▪ If the CHARGER_PRSNT# pin is used, it should be held low for >200us

NVIDIA Jetson TX2 OEM Product Design Guide

JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 18

4.0 GENERAL ROUTING GUIDELINES

Signal Name Conventions

The following conventions are used in describing the signals for Jetson TX2:

▪ Signal names use a mnemonic to represent the function of the signal. For example, Secure Digital Interface #3

Command signal is represented as SDCARD_CMD, written in bold to distinguish it from other text. All active low

signals are identified by a # or an underscore followed by capital N (_N) after the signal name. For example,

RESET_IN# indicates an active low signal. Active high signals do not have the underscore-N (_N) after the signal

names. For example, SDCARD_CMD indicates an active high signal. Differential signals are identified as a pair

with the same names that end with _P & _N, just P & N or + & - (for positive and negative, respectively). For

example, USB1_DP and USB1_DN indicate a differential signal pair.

▪ I/O Type The signal I/O type is represented as a code to indicate the operational characteristics of the signal. The

table below lists the I/O codes used in the signal description tables.

Table 12. Signal Type Codes

Code

Definition

Analog

DIFF I/O

Bidirectional Differential Input/Output

DIFF IN

Differential Input

DIFF OUT

Differential Output

I/O

Bidirectional Input/Output

Input

Output

Open Drain Output

I/OD

Bidirectional Input / Open Drain Output

Power

Routing Guideline Format

The routing guidelines have the following format to specify how a signal should be routed.

▪ Breakout traces are traces routed from a BGA or other pin array, either to a point beyond the array, or to another

layer where full normal spacing guidelines can be met. Breakout trace delay limited to 500 mils unless otherwise

specified.

▪ After breakout, signal should be routed according to specified impedance for differential, single-ended, or both (for

example: HDMI). Trace spacing to other signals also specified.

▪ Follow max & min trace delays where specified. Trace delays are typically shown in mm or in terms of signal delay

in pico-seconds (ps) or both.

- For differential signals, trace spacing to other signals must be larger of specified × dielectric height or inter-

pair spacing

- Spacing to other signals/pairs cannot be smaller than spacing between complementary signals (intra-pair).

- Total trace delay depends on signal velocity which is different between outer (microstrip) & inner (stripline)

layers of a PCB.

NVIDIA Jetson TX2 OEM Product Design Guide

JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 19

Signal Routing Conventions

Throughout this document, the following signal routing conventions are used:

SE Impedance (/ Diff Impedance) at x Dielectric Height Spacing

▪ Single-ended (SE) impedance of trace (along with differential impedance for diff pairs) is achieved by spacing

requirement. Spacing is multiple of dielectric height. Dielectric height is typically different for microstrip & stripline.

Note: 1 mil = 1/1000th of an inch.

Note:

Trace spacing requirement applies to SE traces or differential pairs to other SE traces or differential pairs. It does not apply to

traces making up a differential pair. For this case, spacing/trace widths are chosen to meet differential impedance

requirement.

General Routing Guidelines

Pay close attention when routing high speed interfaces, such as HDMI/DP, USB 3.0, PCIe or DSI/CSI. Each of these interfaces

has strict routing rules for the trace impedance, width, spacing, total delay, and delay/flight time matching. The following

guidelines provide an overview of the routing guidelines and notations used in this document.

▪ Controlled Impedance

Each interface has different trace impedance requirements & spacing to other traces. It is up to designer to

calculate trace width & spacing required to achieve specified single-ended (SE) & differential (Diff) impedances.

Unless otherwise noted, trace impedance values are ±15%.

▪ Max Trace Lengths/Delays

Trace lengths/delays should include main PCB routing and any additional routing on a Flex/ secondary PCB

segment connected to main PCB. The max length/delay should be from Jetson TX2 to the actual connector (i.e.

USB, HDMI, SD Card, etc.) or device (i.e. onboard USB device, Display driver IC, camera imager IC, etc.)

▪ Trace Delay/Flight Time Matching

Signal flight time is the time it takes for a signal to propagate from one end (driver) to other end (receiver). One

way to get same flight time for signal within signal group is to match trace lengths within specified delay in the

signal group.

- Total trace delay = Carrier PCB trace delay only. Do not exceed maximum trace delay specified.

- For six layers or more, it is recommended to match trace delays based on flight time of signals. For example,

outer-layer signal velocity could be 150psi (ps/inch) & inner-layer 180psi. If one signal is routed 10 inches on

outer layer & second signal is routed 10 inches in inner layer, difference in flight time between two signals will

be 300ps! That is a big difference if required matching is 15ps (trace delay matching). To fix this, inner trace

needs to be 1.7 inches shorter or outer trace needs to be 2 inches longer.

- In this design guide, terms such as intra-pair & inter-pair are used when describing differential pair delay.

Intra-pair refers to matching traces within differential pair (for example, true to complement trace matching).

Inter-pair matching refers to matching differential pairs average delays to other differential pairs average

delays.

General PCB Routing Guidelines

For GSSG stack-up to minimize crosstalk, signal should be routed in such a way that they are not on top of each

other in two routing layers (see diagram to right)

Do not route other signals or power traces/areas directly under or over critical high-speed interface signals.

Note:

The requiements detailed in the Interface Signal Routing Requirements tables must be met for

all interfaces implemented or proper operation cannot be guaranteed.

NVIDIA Jetson TX2 OEM Product Design Guide

JETSON TX2 OEM PRODUCT | DESIGN GUIDE | 20170912 20

5.0 USB, PCIE & SATA

The Jetson TX2 allows multiple USB 3.0 & PCIe interfaces, and a single SATA interface to be brought out on the module. In

some cases, these interfaces are multiplexed on some of the module pins. The tables below show several ways to bring out as

many of the USB 3.0 or PCIe interfaces as possible to meet different design requirements. The first table covers many of the

combinations possible on designs built around Jetson TX2 only. The second table covers the combinations possible for both

Jetson TX2 and previous/future pin compatible modules.

Table 13. Jetson TX2 USB 2.0 Pin Descriptions

Pin #

Jetson TX2 Pin Name

Tegra Signal

Usage/Description

Usage on Carrier

Board

Direction

Pin Type

B40

USB0_D–

USB0_DN

USB 2.0 Port 0 Data–

USB 2.0 Micro AB

Bidir

USB PHY

B39

USB0_D+

USB0_DP

USB 2.0 Port 0 Data+

Bidir

A17

USB0_EN_OC#

USB_VBUS_EN0

USB VBUS Enable/Overcurrent 0

Bidir

Open Drain – 3.3V

A36

USB0_OTG_ID

(PMIC GPIO0)

USB 0 ID

Input

Analog

B37

USB0_VBUS_DET

UART5_CTS

USB 0 VBUS Detect

Input

USB VBUS, 5V

A39

USB1_D–

USB1_DN

USB 2.0, Port 1 Data–

USB 3.0 Type A

Bidir

USB PHY

A38

USB1_D+

USB1_DP

USB 2.0, Port 1 Data+

Bidir

A18

USB1_EN_OC#

USB_VBUS_EN1

USB VBUS Enable/Overcurrent 1

Bidir

Open Drain – 3.3V

B43

USB2_D–

USB2_DN

USB 2.0, Port 2 Data–

M.2 Key E

Bidir

USB PHY

B42

USB2_D+

USB2_DP

USB 2.0, Port 2 Data+

Bidir

Table 14. Jetson TX2 USB 3.0, PCIe & SATA Pin Descriptions

Pin #

Jetson TX2 Pin Name

Tegra Signal

Usage/Description

Usage on the Carrier

Board

Direction

Pin Type

A44

PEX0_REFCLK+

PEX_CLK1P

PCIe 0 Reference Clock+ (PCIe IF #0)

PCIe x4 Connector

Output

PCIe PHY

A45

PEX0_REFCLK–

PEX_CLK1N

PCIe 0 Reference Clock – (PCIe IF #0)

Output

C48

PEX0_CLKREQ#

PEX_L0_CLKREQ_N

PCIe 0 Clock Request (PCIe IF #0)

Bidir

Open Drain 3.3V, Pull-up on

the module

C49

PEX0_RST#

PEX_L0_RST_N

PCIe 0 Reset (PCIe IF #0)

Output

H44

PEX0_RX+

PEX_RX4P

PCIe 0 Lane 0 Receive+ (PCIe IF #0)

Input

PCIe PHY, AC-Coupled on

carrier board

H45

PEX0_RX–

PEX_RX4N

PCIe 0 Lane 0 Receive– (PCIe IF #0)

Input

E44

PEX0_TX+

PEX_TX4P

PCIe 0 Lane 0 Transmit+ (PCIe IF #0)

Output

E45

PEX0_TX–

PEX_TX4N

PCIe 0 Lane 0 Transmit– (PCIe IF #0)

Output

G42

USB_SS1_RX+

PEX_RX2P

USB SS 1 Receive+ (USB 3.0 Port #2 or

PCIe IF #0 Lane 1)

Input

G43

USB_SS1_RX–

PEX_RX2N

USB SS 1 Receive– (USB 3.0 Port #2 or

PCIe #0 Lane 1)

Input

D42

USB_SS1_TX+

PEX_TX2P

USB SS 1 Transmit+ (USB 3.0 Port #2 or

PCIe IF #0 Lane 1)

Output

D43

USB_SS1_TX–

PEX_TX2N

USB SS 1 Transmit– (USB 3.0 Port #2 or

PCIe #0 Lane 1)

Output

F40

PEX2_RX+

PEX_RX3P

PCIe 2 Receive+ (PCIe IF #0 Lane 2 or PCIe

IF #1 Lane 0)

Input

F41

PEX2_RX–

PEX_RX3N

PCIe 2 Receive– (PCIe IF #0 Lane 2 or PCIe

IF #1 Lane 0)

Input

C40

PEX2_TX+

PEX_TX3P

PCIe 2 Transmit+ (PCIe IF #0 Lane 2 or

PCIe IF #1 Lane 0)

Output

C41

PEX2_TX–

PEX_TX3N

PCIe 2 Transmit– (PCIe IF #0 Lane 2 or

PCIe IF #1 Lane 0)

Output

G39

PEX_RFU_RX+

PEX_RX1P

PCIe RFU Receive+ (PCIe IF #0 Lane 3 or

USB 3.0 Port #1)

Input

G40

PEX_RFU_RX–

PEX_RX1N

PCIe RFU Receive– (PCIe IF #0 Lane 3 or

USB 3.0 Port #1)

Input

D39

PEX_RFU_TX+

PEX_TX1P

PCIe RFU Transmit+ (PCIe IF #0 Lane 3 or

USB 3.0 Port #1)

Output

D40

PEX_RFU_TX–

PEX_TX1N

PCIe RFU Transmit – (PCIe IF #0 Lane 3 or

USB 3.0 Port #1)

Output

D48

PEX_WAKE#

PEX_WAKE_N

PCIe Wake

PCIe x4 conn & M.2

Input

Open Drain 3.3V, Pull-up on

the module

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