![](https://csdnimg.cn/release/download_crawler_static/17856018/bg13.jpg)
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions
Symbol Type Description
A13, A12/BC#,
A10/AP, A [9:0]
Input Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also pro-
vide the op-code during a LOAD MODE command. Address inputs are referenced to
V
REFCA
. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 69 (page 116).
BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0,
MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are
referenced to V
REFCA
.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is
dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle), or active power-down (row active in any bank). CKE is synchronous for
power-down entry and exit and for self refresh entry. CKE is asynchronous for self re-
fresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled dur-
ing POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during
SELF REFRESH. CKE is referenced to V
REFCA
.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to V
REFCA
.
DM Input Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with the input data during a write access. Although
the DM ball is input-only, the DM loading is designed to match that of the DQ and
DQS balls. DM is referenced to V
REFDQ
. DM has an optional use as TDQS on the x8.
ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,
and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored
if disabled via the LOAD MODE command. ODT is referenced to V
REFCA
.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to V
REFCA
.
RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V
SS
. The RESET# input
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
DD
and
DC LOW ≤ 0.2 × V
DDQ
. RESET# assertion and desertion are asynchronous.
DQ[0:3] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are
referenced to V
REFDQ
.
1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
PDF: CCM005-1005363231-10363
1Gb_DDR3_SDRAM.pdf - Rev. O 9/18 EN
19
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