镁光1.5V DDR3 SDRAM手册：MT41系列详细规格与功能概述

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本文档是镁光公司(Micron Technology)关于1.5V DDR3 SDRAM系列产品的手册，主要包括MT41J256M4、MT41J128M8和MT41J64M16三种内存芯片。这些芯片提供了适用于不同应用场景的规格，如256MB x 4, 128MB x 8, 和 64MB x 16，以满足不同数据传输速度和存储容量的需求。 DDR3 SDRAM的关键特性包括： 1. **工作电压**：这些芯片支持1.5伏特(VDD = VDDQ = 1.5V ± 0.075V)，这意味着它们在低功耗设计中非常适用。 2. **I/O接口**：采用1.5V中心终止推挽式I/O，确保信号的稳定传输，并采用差分双向数据 strobe，提高了数据传输的可靠性。 3. **架构设计**：采用8n位预取（8-bit prefetch）架构，可以加快数据访问速度，减少了延迟。 4. **时钟信号**：支持差分输入时钟(CK, CK#)，提供精确的时间控制。 5. **内部银行**：内存芯片有8个内置银行，允许并发的数据读写操作，提高了整体系统性能。 6. **动态和静态确定** (ODT): 提供了可编程的CAS (Column Address Strobe) 读取、写入延迟时间和数据mask信号的控制，以适应不同的工作模式。 7. **可编程延迟**：CAS latency (CL), POSTED CAS ADDITIVE latency (AL), 和 CAS write latency (CWL) 可根据tCK进行设置，灵活性高。 8. **内存模式**：支持固定的8字节突发长度(BL)和4字节突发切片(BC)，通过模制寄存器集(MRS)实现动态调整。 9. **功能特性**：具备自刷新模式，以及温度依赖的自动自刷新(ASR)能力，确保在不同温度下内存的正常运行。 10. **优化技术**：包括写级别调整、多功能寄存器以及输出驱动器校准，以优化信号质量和降低功耗。 11. **封装选项**：手册提供了多种封装形式，包括无铅FBGA封装，如78球、96球，尺寸分别为8mm x 11.5mm或8mm x 14mm，满足不同应用的封装需求。这份手册详细介绍了镁光1.5V DDR3 SDRAM的电气规格、性能参数和操作模式，为设计者提供了全面的技术参考，无论是系统设计师还是硬件工程师，在选择和配置此类内存组件时都将非常有用。

Figure 4: 128 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[13:0]

BA[2:0]

Address

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(16,384 x 128 x 64)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

READ

drivers

DQ[7:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

DM/TDQS

(shared pin)

TDQS#

CK, CK#

DQS, DQS#

ZQ CAL

RZQ

CK, CK#

RAS#

WE#

CAS#

CS#

ODT

CKE

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

sw1

sw2

DDQ

TT,nom

TT(WR)

sw1

sw2

DDQ

TT,nom

TT(WR)

sw1

sw2

DDQ

TT,nom

TT(WR)

BC4 (burst chop)

BC4

WRITE

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128

x64)

ODT

control

SSQ

A12

OTF

Figure 5: 64 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[12:0]

BA[2:0]

Address

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(8192 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

8,192

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ

drivers

DQ[15:0]

READ

FIFO

and

data

MUX

Data

BC4 (burst chop)

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

sw1

sw2

DDQ

TT,nom

TT(WR)

BC4

sw1

sw2

DDQ

TT,nom

TT(WR)

sw1

sw2

DDQ

TT,nom

TT(WR)

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

SSQ

A12

OTF

1Gb: x4, x8, x16 DDR3 SDRAM

Functional Block Diagrams

PDF: CCM005-1005363231-10363

1Gb_DDR3_SDRAM.pdf - Rev. O 9/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A13, A12/BC#,

A10/AP, A [9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank (A10

LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also pro-

vide the op-code during a LOAD MODE command. Address inputs are referenced to

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 69 (page 116).

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE,

or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0,

MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are

referenced to V

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of CK#.

Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is

dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE

LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks

idle), or active power-down (row active in any bank). CKE is synchronous for

power-down entry and exit and for self refresh entry. CKE is asynchronous for self re-

fresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled dur-

ing POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during

SELF REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access. Although

the DM ball is input-only, the DM loading is designed to match that of the DQ and

DQS balls. DM is referenced to V

REFDQ

. DM has an optional use as TDQS on the x8.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,

and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored

if disabled via the LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input

receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

and

DC LOW ≤ 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

DQ[0:3] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are

referenced to V

REFDQ

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: CCM005-1005363231-10363

1Gb_DDR3_SDRAM.pdf - Rev. O 9/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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