Maxim DS12887：非易失时钟芯片数据手册，全面特性与接口介绍
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更新于2024-08-02
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本文档是Maxim公司的DS12887实时时钟芯片数据手册，为IBM计算机时钟/日历系统提供了一个方便的替代方案。这款芯片具有以下关键特性：
1. **兼容性**：DS12887与MC146818B和DS1287型号的引脚兼容，方便在现有设计中轻松替换，减少了集成成本。
2. **非易失性存储**：该芯片完全是非挥发性的，即使在无电源情况下也能维持超过10年的精确计时，确保了长期稳定性。
3. **内置子系统**：包含锂离子电池、石英振荡器以及支持电路，构成一个完整的独立时钟和日历系统。
4. **时间与日期管理**：能准确地记录秒、分、时、天、星期、日期、月份和年份，包括闰年补偿，直到2100年。
5. **多种显示选项**：支持二进制或BCD（二进制补码代码）表示，可选择12小时或24小时制，并区分上午和下午。
6. **时间调整功能**：提供夏令时选项，适应不同地区的季节性时间调整。
7. **接口灵活性**：可以配置为兼容摩托罗拉或英特尔总线标准，提高与不同硬件平台的兼容性。
8. **高效通信**：采用多路复用总线，优化了引脚利用，提高了系统的能源效率。
9. **内存映射**：通过软件将时钟和控制寄存器映射为128位RAM地址，方便编程和数据访问。
10. **扩展功能**：包含14字节的时钟和控制寄存器，以及114字节的一般用途RAM，提供了丰富的存储空间。
11. **输出信号**：具有可编程的方波输出信号，可用于外部设备同步。
12. **中断管理**：有三个中断源，分别可软件屏蔽和测试，支持时间报时警报、周期性事件计时等功能，频率范围从122毫秒到500毫秒。
13. **接口信号**：提供与软件交互的中断请求信号（IRQ），便于外部处理程序响应时钟事件。
14. **pin assignment**：文档详细列出了AD0-AD7作为地址/数据总线，MOT用于选择总线类型，CS用于时钟信号。
这些特性使得DS12887成为工业级应用的理想选择，适用于需要精确时间管理的设备，如嵌入式系统、仪表、通讯设备等。通过深入了解这个数据手册，设计师可以充分利用DS12887的功能来构建更精确、可靠的时间和日期管理系统。
DS12887
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occurs on the AS bus will clear the address regardless of whether CS is asserted. Access commands
should be sent in pairs.
DS (Data Strobe or Read Input) – The DS/RD pin has two modes of operation depending on the level
of the MOT pin. When the MOT pin is connected to V
CC
, Motorola bus timing is selected. In this mode
DS is a positive pulse during the latter portion of the bus cycle and is called Data Strobe. During read
cycles, DS signifies the time that the DS12887 is to drive the bidirectional bus. In write cycles the trailing
edge of DS causes the DS12887 to latch the written data. When the MOT pin is connected to GND, Intel
bus timing is selected. In this mode the DS pin is called Read (RD ).RD identifies the time period when
the DS12887 drives the bus with read data. The RD signal is the same definition as the Output Enable
(OE ) signal on a typical memory.
R/W (Read/Write Input) – The R/ W pin also has two modes of operation. When the MOT pin is
connected to V
CC
for Motorola timing, R/ W is at a level which indicates whether the current cycle is a
read or write. A read cycle is indicated with a high level on R/ W while DS is high. A write cycle is
indicated when R/ W is low during DS.
When the MOT pin is connected to GND for Intel timing, the R/ W signal is an active low signal called
WR. In this mode the R/ W pin has the same meaning as the Write Enable signal ( WE ) on generic RAMs.
CS (Chip Select Input) – The Chip Select signal must be asserted low for a bus cycle in the DS12887 to
be accessed. CS must be kept in the active state during DS and AS for Motorola timing and during RD
and WR for Intel timing. Bus cycles which take place without asserting CS will latch addresses but no
access will occur. When V
CC
is below 4.25 volts, the DS12887 internally inhibits access cycles by
internally disabling the CS input. This action protects both the real time clock data and RAM data during
power outages.
IRQ (Interrupt Request Output) – The IRQ pin is an active low output of the DS12887 that can be
used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the
interrupt is present and the corresponding interrupt–enable bit is set. To clear the IRQ pin the processor
program normally reads the C register. The RESET pin also clears pending interrupts.
When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple
interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an
external pullup resistor.
RESET (Reset Input) – The RESET pin has no effect on the clock, calendar, or RAM. On power–up the
RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of time
that RESET is held low is dependent on the application. However, if RESET is used on power–up, the
time RESET is low should exceed 200 ms to make sure that the internal timer that controls the DS12887
on power-up has timed out. When RESET is low and V
CC
is above 4.25 volts, the following occurs:
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