Marvell 88W8686 WiFi芯片手册：集成MAC/Baseband/RF低功耗SoC

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"Marvell的88W8686是一款集成MAC、基带和射频低功耗SoC芯片，适用于无线Wi-Fi网络，支持IEEE 802.11a/g/b标准。该芯片的手册是Marvell公司的一份机密资料，仅在保密协议下分发，版本号为MV-S103343-00，修订版为D，发布日期为2007年2月20日。文档中包含了关于芯片的重要信息、注意事项以及安全警告，强调了对硬件、软件和数据保护的重要性。" Marvell的88W8686芯片是一款专为Wi-Fi应用设计的高性能集成电路，它集成了媒体访问控制器（MAC）、基带处理器和射频（RF）功能，形成一个完整的低功耗系统级芯片（SoC）。这款芯片支持多种无线局域网（WLAN）标准，特别是IEEE 802.11a/g/b，这些标准定义了不同速率和频段的无线通信，使其能够在家庭、办公室和公共网络环境中提供无线连接。文档中的“Note”、“Caution”和“Warning”是重要的提示符号，它们分别提供了相关的信息、可能对硬件或软件造成损害的警告，以及可能导致人身伤害的风险警示。这表明在处理和使用88W8686芯片时，必须遵循严格的操作指南和安全规定，以确保设备的正常运行和人员的安全。文档的状态部分提到，其版本为2.00，技术出版物编号为0.xx，这意味着这是一个不断更新和完善的文档。用户应定期查看Marvell公司的官方网站获取最新的技术信息和更新。值得注意的是，该文档明确指出，未经Marvell公司许可，不得以任何形式复制或传播此文档的任何部分，无论是电子方式还是机械方式，包括但不限于影印和录制。这强调了Marvell对其知识产权的保护力度，也表明了用户在使用该芯片和参考手册时应尊重并遵守版权法规。 Marvell的88W8686芯片是Wi-Fi解决方案的关键组成部分，具有高度集成和低功耗的特点。了解和掌握这份datasheet对于设计和开发基于88W8686的无线产品至关重要，同时，用户在使用过程中必须遵循严格的使用和保密条款。

88W8686

Datasheet

Doc. No. MV-S103343-00 Rev. D

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Doc. No. MV-S103343-00 Rev. D

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List of Tables

Section 1.Package and Power........................................................................................ 21

Table 1: Flip Chip Locations—280 μm Pitch...................................................................................................25

Table 2: Flip Chip Locations—500 μm Pitch...................................................................................................30

Table 3: Pin Types..........................................................................................................................................35

Table 4: WLAN RF/Network Interface............................................................................................................35

Table 5: Baseband Interface...........................................................................................................................36

Table 6: Host Interfaces–G-SPI/SDIO............................................................................................................38

Table 7: Bluetooth Coexistence Interface.......................................................................................................39

Table 8: EEPROM Serial Control...................................................................................................................40

Table 9: GPIO/LED Control............................................................................................................................40

Table 10: Joint Test Action Group (JTAG) and Test Interface..........................................................................41

Table 11: Control and Power Down..................................................................................................................42

Table 12: Power and Ground............................................................................................................................42

Table 13: Reserved..........................................................................................................................................43

Table 14: VDD18A Supply................................................................................................................................44

Table 15: VDD18_LDO Supply.........................................................................................................................44

Table 16: VDD30 Supply..................................................................................................................................44

Table 17: VIO_X1 Supply.................................................................................................................................45

Table 18: VIO_X2 Supply.................................................................................................................................45

Table 19: VDD18_LDO and VDD12 Power Supply Configurations..................................................................46

Table 20: Tri-State Floating..............................................................................................................................47

Table 21: Output Low.......................................................................................................................................47

Table 22: Output High.......................................................................................................................................47

Section 2.Processor......................................................................................................... 49

Table 23: DMA Registers..................................................................................................................................51

Table 24: Interrupt Register (IRQ and FIQ) Mapping in Interrupt Controller Unit.............................................57

Table 25: Configuration Pins............................................................................................................................60

Section 3.Network Functions.......................................................................................... 61

Table 26: MAC Timing Intervals.......................................................................................................................65

Table 27: QoS Queues.....................................................................................................................................67

Table 28: 802.11g Channels Supported...........................................................................................................76

Table 29: 802.11a Channels Supported...........................................................................................................77

Table 30: 802.11h Channels Supported...........................................................................................................77

Table 31: 802.11j Channels Supported (Japan)...............................................................................................78

Table 32: Mode Select......................................................................................................................................79

Table 33: RF Radio Channel Frequency Registers..........................................................................................83

Table 34: 19.2 MHz Reference Frequency.......................................................................................................84

Table 35: 20 MHz Reference Frequency..........................................................................................................86

88W8686

Datasheet

Doc. No. MV-S103343-00 Rev. D

CONFIDENTIAL

Page 18 Document Classification: Proprietary February 20, 2007, 2.00

Table 36: 24 MHz Reference Frequency.........................................................................................................88

Table 37: 26 MHz Reference Frequency.........................................................................................................90

Table 38: 38.4 MHz Reference Frequency......................................................................................................92

Table 39: 40 MHz Reference Frequency.........................................................................................................94

Table 40: CCMP/AES Registers......................................................................................................................97

Table 41: TKIP/WEP Registers........................................................................................................................98

Table 42: BCA Registers...............................................................................................................................102

Table 43: Single Antenna Default Arbitration Table.......................................................................................107

Table 44: Dual Antenna Default Arbitration Table.........................................................................................107

Table 45: Arbiter Decision Table (BT_FREQ_OOB Bit = 1, Always InBand).................................................110

Table 46: Arbiter Decision Table, Bluetooth 1.2 Device (BT_FREQ_OOB Bit = 0, Always OutofBand)........111

Table 47: Arbiter Decision Table, Bluetooth 1.2/1.1 Device..........................................................................112

Table 48: Arbitration Table Variables.............................................................................................................112

Table 49: SM Input Ports and States.............................................................................................................113

Table 50: SM Port List...................................................................................................................................114

Section 4.Host Interfaces.............................................................................................. 115

Table 51: G-SPI Interface Description...........................................................................................................116

Table 52: G-SPI Interface Registers Memory Space.....................................................................................121

Table 53: Internal SQU Memory Space.........................................................................................................122

Table 54: SDIO Interface Signal Description.................................................................................................125

Table 55: SDIO Electrical Function Definition................................................................................................127

Table 56: SDIO Mode, SDIO Commands......................................................................................................128

Table 57: SPI Mode, SDIO Commands.........................................................................................................128

Table 58: SDIO Registers..............................................................................................................................129

Section 5.Peripheral Bus Interface............................................................................... 131

Table 59: TWSI Registers..............................................................................................................................133

Table 60: 1-Wire Interface Registers.............................................................................................................136

Table 61: SPI EEPROM Interface Description...............................................................................................137

Table 62: Write and Read Sequence Registers.............................................................................................138

Table 63: UART Clock Divisor.......................................................................................................................141

Table 64: UART Pin Definitions.....................................................................................................................142

Table 65: UART Boot Requirements.............................................................................................................142

Table 66: GPIO Functions.............................................................................................................................144

Section 6.Electrical Specifications............................................................................... 145

Table 67: Absolute Maximum Ratings...........................................................................................................145

Table 68: Operating Conditions.....................................................................................................................146

Table 69: Internal Operating Frequencies.....................................................................................................146

Table 70: DC Electricals—3V Pads (VDD30)................................................................................................147

Table 71: DC Electricals—1.8V/3.3V (VIO_X1/VIO_X2)................................................................................147

Table 72: Thermal Conditions—68-Pin (8x8x1mm)......................................................................................149

Table 73: Flip Chip Thermal Conditions—280 μm Pitch................................................................................150

CONFIDENTIAL

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Table 74: Flip Chip Thermal Conditions—500 μm Pitch.................................................................................150

Table 75: External Timing Requirements (RESETn Pin)................................................................................151

Table 76: Internal Reset Timing......................................................................................................................151

Table 77: Configuration Pin Serial Interface...................................................................................................152

Table 78: DC Coupled Mode..........................................................................................................................153

Table 79: AC Coupled Mode..........................................................................................................................153

Table 80: Phase Noise...................................................................................................................................153

Table 81: 19.2 MHz Clock Timing...................................................................................................................154

Table 82: 20 MHz Clock Timing......................................................................................................................154

Table 83: 24 MHz Clock Timing......................................................................................................................154

Table 84: 26 MHz Clock Timing......................................................................................................................154

Table 85: 38.4 MHz Clock Timing...................................................................................................................155

Table 86: 40 MHz Clock Timing......................................................................................................................155

Table 87: Sleep Clock Timing.........................................................................................................................156

Table 88: Crystal Specifications.....................................................................................................................156

Table 89: 802.11g/b LNA and Rx RF Mixer....................................................................................................157

Table 90: 802.11g/b RBB...............................................................................................................................158

Table 91: 802.11a LNA and Rx RF Mixer.......................................................................................................159

Table 92: 802.11a RBB..................................................................................................................................160

Table 93: Tx Mode..........................................................................................................................................161

Table 94: Local Oscillator...............................................................................................................................161

Table 95: SPI Host Interface Timing Data......................................................................................................163

Table 96: SDIO Timing Data...........................................................................................................................165

Table 97: Serial Interface Timing Data...........................................................................................................167

Table 98: LED Mode.......................................................................................................................................168

Table 99: JTAG Timing...................................................................................................................................169

Table 100: VDD12 Current Consumption.........................................................................................................170

Table 101: VDD18A Current Consumption.......................................................................................................171

Table 102: VDD18_LDO Current Consumption................................................................................................172

Table 103: VDD30 Current Consumption.........................................................................................................173

Table 104: VIO_X1 Current Consumption........................................................................................................173

Table 105: VIO_X2 Current Consumption........................................................................................................174

Section 7.Part Order Numbering/Package Marking.................................................... 175

Table 106: Part Order Options..........................................................................................................................175

Appendix A.Flip Chip Underfill Requirement............................................................... 177

Table 107: Solder Bump Composition Values..................................................................................................177

Table 108: Pad Guideline Values.....................................................................................................................180

Appendix B.Acronyms and Abbreviations................................................................... 181

Table 109: Acronyms and Abbreviations..........................................................................................................181

Appendix C.Revision History........................................................................................ 189

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