IEEE 2005 Verilog HDL官方手册：设计与应用指南

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A.5.4 UDP instantiation.......................................................................................................... 771

A.6 Behavioral statements.............................................................................................................. 771

A.6.1 Continuous assignment statements ............................................................................... 771

A.6.2 Procedural blocks and assignments............................................................................... 771

A.6.3 Parallel and sequential blocks....................................................................................... 772

A.6.4 Statements..................................................................................................................... 772

A.6.5 Timing control statements............................................................................................. 772

A.6.6 Conditional statements.................................................................................................. 773

A.6.7 Case statements............................................................................................................. 773

A.6.8 Looping statements ....................................................................................................... 774

A.6.9 Task enable statements.................................................................................................. 774

A.7 Specify section......................................................................................................................... 774

A.7.1 Specify block declaration.............................................................................................. 774

A.7.2 Specify path declarations .............................................................................................. 774

A.7.3 Specify block terminals................................................................................................. 775

A.7.4 Specify path delays ....................................................................................................... 775

A.7.5 System timing checks.................................................................................................... 776

A.8 Expressions .............................................................................................................................. 778

A.8.1 Concatenations.............................................................................................................. 778

A.8.2 Function calls................................................................................................................ 778

A.8.3 Expressions ................................................................................................................... 778

A.8.4 Primaries ....................................................................................................................... 779

A.8.5 Expression left-side values............................................................................................ 780

A.8.6 Operators....................................................................................................................... 780

A.8.7 Numbers........................................................................................................................ 780

A.8.8 Strings ........................................................................................................................... 781

A.9 General..................................................................................................................................... 781

A.9.1 Attributes....................................................................................................................... 781

A.9.2 Comments ..................................................................................................................... 781

A.9.3 Identifiers ...................................................................................................................... 782

A.9.4 White space................................................................................................................... 783

Annex B (normative) List of keywords ....................................................................................................... 784

Annex C (informative) System tasks and functions .................................................................................... 786

C.1 $countdrivers............................................................................................................................ 786

C.2 $getpattern................................................................................................................................ 787

C.3 $input ....................................................................................................................................... 788

C.4 $key and $nokey ...................................................................................................................... 788

C.5 $list........................................................................................................................................... 789

C.6 $log and $nolog........................................................................................................................ 789

C.7 $reset, $reset_count, and $reset_value..................................................................................... 789

C.8 $save, $restart, and $incsave.................................................................................................... 790

C.9 $scale........................................................................................................................................ 791

C.10$scope ...................................................................................................................................... 791

C.11$showscopes ............................................................................................................................ 791

C.12$showvars ................................................................................................................................ 792

C.13$sreadmemb and $sreadmemh................................................................................................. 792

Annex D (informative) Compiler directives................................................................................................ 793

D.1 `default_decay_time................................................................................................................. 793

D.2 `default_trireg_strength............................................................................................................ 793

This is an unapproved IEEE Standards Draft, subject to change.

DRAFT STANDARD VERILOG

HARDWARE DESCRIPTION LANGUAGE IEEE P1364-2005/D3, 1/7/04

Draft Standard Verilog

Hardware

Description Language

1. Overview

1.1 Objectives of this standard

The intent of this standard is to serve as a complete specification of the Verilog

Hardware Description Lan-

guage (HDL). This document contains

— The formal syntax and semantics of all Verilog HDL constructs

— The formal syntax and semantics of Standard Delay Format (SDF) constructs

— Simulation system tasks and functions, such as text output display commands

— Compiler directives, such as text substitution macros and simulation time scaling

— The Programming Language Interface (PLI) binding mechanism

— The formal syntax and semantics of access routines, task/function routines, and Verilog procedural

interface routines

— Informative usage examples

— Informative delay model for SDF

— Listings of header files for PLI

1.2 Conventions used in this standard

This standard is organized into clauses, each of which focuses on a specific area of the language. There are

subclauses within each clause to discuss individual constructs and concepts. The discussion begins with an

introduction and an optional rationale for the construct or the concept, followed by syntax and semantic

descriptions, followed by some examples and notes.

The term shall is used throughout this standard to indicate mandatory requirements, whereas the term can is

used to indicate optional features. These terms denote different meanings to different readers of this

standard:

a) To the developers of tools that process the Verilog HDL, the term shall denotes a requirement that

the standard imposes. The resulting implementation is required to enforce the requirements and to

issue an error if the requirement is not met by the input.

b) To the Verilog HDL model developer, the term shall denotes that the characteristics of the Verilog

HDL are natural consequences of the language definition. The model developer is required to adhere

to the constraint implied by the characteristic. The term can denotes optional features that the model

DRAFT STANDARD VERILOG

HARDWARE DESCRIPTION LANGUAGE IEEE P1364-2005/D3, 1/7/04

This is an unapproved IEEE Standards Draft, subject to change.

developer can exercise at discretion. If used, however, the model developer is required to follow the

requirements set forth by the language definition.

c) To the Verilog HDL model user, the term shall denotes that the characteristics of the models are nat-

ural consequences of the language definition. The model user can depend on the characteristics of

the model implied by its Verilog HDL source text.

1.3 Syntactic description

The formal syntax of the Verilog HDL is described using Backus-Naur Form (BNF). The following conven-

tions are used:

a) Lowercase words, some containing embedded underscores, are used to denote syntactic categories.

For example:

module_declaration

b) Boldface words are used to denote reserved keywords, operators, and punctuation marks as a

required part of the syntax. For example:

module => ;

c) A vertical bar separates alternative items unless it appears in boldface, in which case it stands for

itself. For example:

unary_operator ::=

+ | - | ! | ~ | & | ~& | | | ~| | ^ | ~^ | ^~

d) Square brackets enclose optional items. For example:

input_declaration ::= input [range] list_of_variables

;

e) Braces enclose a repeated item unless it appears in boldface, in which case it stands for itself. The

item may appear zero or more times; the repetitions occur from left to right as with an equivalent

left-recursive rule. Thus, the following two rules are equivalent:

list_of_param_assignments ::= param_assignment { , param_assignment }

list_of_param_assignments ::=

param_assignment

| list_of_param_assignment , param_assignment

f) If the name of any category starts with an italicized part, it is equivalent to the category name

without the italicized part. The italicized part is intended to convey some semantic information. For

example, "msb_index" and "lsb_index" are equivalent to "index".

The main text uses italicized font when a term is being defined, and constant-width font for examples,

file names, and while referring to constants, especially 0, 1, x, and z values.

1.4 Contents of this standard

A synopsis of the clauses and annexes is presented as a quick reference. There are 27 clauses and 8 annexes.

All clauses, as well as Annex A, Annex B, Annex E, Annex F, and Annex G, are normative parts of this

standard. Annex C, Annex D, and Annex H are included for informative purposes only.

Clause 1—Overview: This clause discusses the conventions used in this standard and its contents.

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