Marvell Alaska 88E1111集成以太网收发器数据手册
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更新于2024-07-09
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88E1111是一款Marvell Alaska系列的集成10/100/1000 Ultra Gigabit Ethernet Transceiver（以太网收发器）。该数据手册，Doc.No.MV-S100649-00Rev.M，发布日期为2020年8月31日，是公开文档，适用于Marvell自家产品的设计或集成。Marvell明确声明，提供此文档不作任何保证，无论是明示的还是默示的，包括但不限于商品质量、特定用途适用性、非侵权性的保证。
这份详细的数据手册涵盖了以下关键知识点：
1. **功能特性**：88E1111支持超高速10/100/1000 Mbps的以太网通信，适用于对网络性能有高要求的应用环境，如数据中心、企业级网络设备和高性能路由器等。
2. **技术规格**：手册列出了接收器和发射器的电气参数、数据传输速率、信号质量指标以及可能支持的协议标准（如IEEE 802.3ab/ae等）。
3. **兼容性与接口**：用户需要确保产品设计与88E1111的接口兼容，并遵循文档中关于引脚定义、电源需求和信号线配置的要求。
4. **安全与合规**：强调了知识产权保护，表明使用本数据手册中的信息仅限于Marvell产品，且用户需自行承担设计和构建过程中可能产生的责任，确保产品的合法性和合规性。
5. **保修与责任**：Marvell及其关联公司明确表示，不提供任何形式的保修或保证，用户需自行判断其应用是否适合。
6. **使用限制**：文档中的软件或固件仅用于Marvell产品，未经授权不能用于其他目的，用户需要自行负责根据提供的信息设计或构建产品。
88E1111数据手册提供了关于这款高性能以太网收发器的关键技术细节，对于任何打算采用它进行产品设计的工程师或技术人员来说，都是必不可少的设计参考资料。在使用前，务必仔细阅读并理解其中的各项限制和注意事项。
Doc. No. MV-S100649-00 Rev. M Copyright © 2020 Marvell
Page 16 Document Classification: Public August 31, 2020
Alaska 88E1111
Datasheet
Figure 37: PMOS Output Impedance (2.5V) Trend Line..................................................................................108
Figure 38: NMOS Output Impedance (2.5V) Trend Line .................................................................................108
Figure 39: Signal Reflections, using the 50 ohm Setting, 60 ohm line.............................................................109
Figure 40: Clean signal after manual calibration for the 60 ohm .....................................................................109
Figure 41: Single LED Connection...................................................................................................................111
Figure 42: Bi-Color LED Connection................................................................................................................111
3 Register Description.......................................................................................................................121
Figure 43: Register Map Summary .................................................................................................................122
4 Electrical Specifications ................................................................................................................ 183
Figure 44: CML I/Os.........................................................................................................................................197
Figure 45: AC connections (CML or LVDS receiver) or DC connection LVDS receiver ..................................199
Figure 46: DC connection to a CML receiver ...................................................................................................200
Figure 47: Input Differential Hysteresis............................................................................................................201
Figure 48: Reset Timing...................................................................................................................................203
Figure 49: XTAL1 Input Clock Timing ..............................................................................................................204
Figure 50: 125CLK Output Timing ...................................................................................................................205
Figure 51: GMII Transmit Timing .....................................................................................................................206
Figure 52: GMII Receive Timing ......................................................................................................................207
Figure 53: 10/100 Mbps Transmit Timing ........................................................................................................208
Figure 54: 10/100 Mbps Receive Timing .........................................................................................................209
Figure 55: TBI Transmit Timing .......................................................................................................................210
Figure 56: TBI Receive Timing ........................................................................................................................211
Figure 57: RGMII/RTBI Multiplexing and Timing .............................................................................................212
Figure 58: GTX_CLK Delay Timing - Register 20.1 = 0...................................................................................213
Figure 59: GTX_CLK Delay Timing - Register 20.1 = 1 (add delay)................................................................213
Figure 60: RGMII RX_CLK Delay Timing - Register 20.7 = 0..........................................................................214
Figure 61: RGMII RX_CLK Delay Timing - Register 20.7 = 1 (add delay).......................................................214
Figure 62: Serial Interface Rise and Fall Times...............................................................................................215
Figure 63: GMII/MII to 10/100/1000BASE-T Transmit Latency Timing............................................................217
Figure 64: 10/100/1000BASE-T to GMII/MII Receive Latency Timing.............................................................219
Figure 65: GMII to 1000BASE-X Transmit Latency Timing .............................................................................220
Figure 66: 1000BASE-X to GMII Receive Latency Timing ..............................................................................221
Figure 67: RGMII/MII to 10/100/1000BASE-T Transmit Latency Timing .........................................................222
Figure 68: 10/100/1000BASE-T to RGMII Receive Latency Timing ................................................................223
Figure 69: RGMII to 1000BASE-X Transmit Latency Timing ..........................................................................
.224
Figure 70: 1000BASE-X to RGMII Receive Latency Timing............................................................................225
Figure 71: TBI to 100BASE-T Transmit Latency Timing..................................................................................226
Figure 72: 1000BASE-T to TBI Receive Latency Timing .................................................................................227
Figure 73: RTBI to 1000BASE-T Transmit Latency Timing .............................................................................228
Figure 74: 1000BASE-T to RTBI Receive Latency Timing ..............................................................................228
Figure 75: SGMII to 10/100/1000BASE-T Transmit Latency Timing ...............................................................229
Figure 76: 10/100/1000BASE-T to SGMII Receive Latency Timing ................................................................230
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