Intel Quartus Prime SCFIFO & DCFIFO用户指南

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"这是Altera公司提供的关于SCFIFO和DCFIFO IP核的手册，适用于Intel Quartus Prime Design Suite 17.1版本。文档详细介绍了这些FIFO（First In First Out，先进先出）存储器的核心特性、配置方法、信号接口、参数设置、功能时序要求以及在时钟域跨越中的应用示例。" 在数字系统设计中，FIFO是一种常用的数据缓冲机制，用于存储和管理数据流，确保数据的正确传输。SCFIFO（Single Clock FIFO）和DCFIFO（Dual Clock FIFO）是两种不同类型的FIFO，主要区别在于它们处理时钟域交叉的方式。 SCFIFO和DCFIFO的配置方法包括通过Verilog HDL原型和VHDL组件声明来定义，同时需要考虑VHDL库和使用的声明。手册中详细列出了这两类FIFO的信号接口，包括输入、输出和控制信号，这些信号用于读写操作、状态指示和错误管理。在参数设置方面，手册涵盖了各种参数选项，如深度、宽度、读写策略等。这些参数可以根据设计需求进行定制，以满足特定系统的性能和资源利用率要求。例如，SCFIFO和DCFIFO的ALMOST_EMPTY功能提供了接近空状态的信号，帮助用户适时地管理读取操作。手册还详细阐述了SCFIFO和DCFIFO的功能时序要求，特别是ALMOST_EMPTY信号的时序以及输出状态标志和延迟。在多时钟域应用中，FIFO通常需要处理 metastability（ metastable 状态）问题，手册中给出了相关的保护措施和选项。针对异步清除和同步清除，手册解释了它们对FIFO操作的影响，并提醒用户注意恢复和去除时间违规警告。此外，SCFIFO和DCFIFO的Show-Ahead模式可以提高数据传输效率，但需谨慎处理不同输入和输出宽度的情况。 DCFIFO的时钟约束设置是另一个关键部分，包括嵌入式和用户可配置的时序约束。手册提供了编码实例，指导用户如何手动实例化这些FIFO，并展示了一个跨时钟域的格雷码计数器传输设计示例，以帮助理解在实际设计中如何应用这些FIFO。最后，手册还提到了嵌入式内存的错误检查和校正（ECC）功能的使用指南，这对于保证数据的完整性至关重要。这份手册是理解和应用Altera的SCFIFO和DCFIFO IP核的宝贵资源，对于进行高性能、低延迟的跨时钟域数据传输设计具有重要价值。

Port Type Required Description

Use to synchronize the following ports:

•

rdreq

•

rdfull

•

rdempty

•

rdusedw

data

(4)

Input Yes

Holds the data to be written in the FIFO IP core when the wrreq

signal is asserted. If you manually instantiate the FIFO IP core,

ensure the port width is equal to the lpm_width parameter.

wrreq

(4)

Input Yes Assert this signal to request for a write operation.

Ensure that the following conditions are met:

•

Do not assert the wrreq signal when the full (for SCFIFO) or

wrfull (for DCFIFO) port is high. Enable the overflow

protection circuitry or set the overflow_checking parameter

to ON so that the FIFO IP core can automatically disable the

wrreq signal when it is full.

•

The wrreq signal must meet the functional timing requirement

based on the full or wrfull signal.

•

Do not assert the wrreq signal during the deassertion of the

aclr signal. Violating this requirement creates a race condition

between the falling edge of the aclr signal and the rising edge

of the write clock if the wrreq port is set to high. For both the

DCFIFO IP cores that target Stratix and Cyclone series, you

have the option to automatically add a circuit to synchronize

the aclr signal with the wrclk clock, or set the

write_aclr_synch parameter to ON. Use this option to

ensure that the restriction is obeyed.

rdreq

(4)

Input Yes

Assert this signal to request for a read operation. The rdreq

signal acts differently in normal mode and show-ahead mode.

Ensure that the following conditions are met:

•

Do not assert the rdreq signal when the empty (for SCFIFO)

or rdempty (for DCFIFO) port is high. Enable the underflow

protection circuitry or set the underflow_checking

parameter to ON so that the FIFO IP core can automatically

disable the rdreq signal when it is empty.

•

The rdreq signal must meet the functional timing requirement

based on the empty or rdempty signal.

sclr

(2)

aclr

(4)

Input No Assert this signal to clear all the output status ports, but the effect

on the q output may vary for different FIFO configurations.

There are no minimum number of clock cycles for aclr signals

that must remain active.

(4)

Output Yes Shows the data read from the read request operation.

For the SCFIFO IP core and DCFIFO IP core, the width of the q

port must be equal to the width of the data port. If you manually

instantiate the IP cores, ensure that the port width is equal to the

lpm_width parameter.

For the DCFIFO_MIXED_WIDTHS IP core, the width of the q port

can be different from the width of the data port. If you manually

instantiate the IP core, ensure that the width of the q port is equal

to the lpm_width_r parameter. The IP core supports a wide write

port with a narrow read port, and vice versa. However, the width

ratio is restricted by the type of RAM block, and in general, are in

the power of 2.

continued...

(4)

Applicable for the SCFIFO, DCFIFO, and DCFIFO_MIXED_WIDTH IP cores.

SCFIFO and DCFIFO IP Cores User Guide

UG-MFNALT_FIFO | 2017.11.06

SCFIFO and DCFIFO IP Cores User Guide

Port Type Required Description

full

(2)

wrfull

(3)

(5)

rdfull

(3)

(5)

Output No When asserted, the FIFO IP core is considered full. Do not perform

write request operation when the FIFO IP core is full.

In general, the rdfull signal is a delayed version of the wrfull

signal. However, for Stratix III devices and later, the rdfull

signal function as a combinational output instead of a derived

version of the wrfull signal. Therefore, you must always refer to

the wrfull port to ensure whether or not a valid write request

operation can be performed, regardless of the target device.

empty

(2)

wrempty

(3)

(5)

rdempty

(3)

(5)

Output No When asserted, the FIFO IP core is considered empty. Do not

perform read request operation when the FIFO IP core is empty.

In general, the wrempty signal is a delayed version of the

rdempty signal. However, for Stratix III devices and later, the

wrempty signal function as a combinational output instead of a

derived version of the rdempty signal. Therefore, you must

always refer to the rdempty port to ensure whether or not a valid

read request operation can be performed, regardless of the target

device.

almost_full

(2)

Output No

Asserted when the usedw signal is greater than or equal to the

almost_full_value parameter. It is used as an early indication

of the full signal.

almost_empty

(2)

Output No

Asserted when the usedw signal is less than the

almost_empty_value parameter. It is used as an early

indication of the empty signal.

(6)

usedw

(2)

wrusedw

(3)

(5)

rdusedw

(3)

(5)

Output No Show the number of words stored in the FIFO.

Ensure that the port width is equal to the lpm_widthu parameter

if you manually instantiate the SCFIFO IP core or the DCFIFO IP

core. For the DCFIFO_MIXED_WIDTH IP core, the width of the

wrusedw and rdusedw ports must be equal to the LPM_WIDTHU

and lpm_widthu_r parameters respectively.

For Stratix, Stratix GX, and Cyclone devices, the FIFO IP core

shows full even before the number of words stored reaches its

maximum value. Therefore, you must always refer to the full or

wrfull port for valid write request operation, and the empty or

rdempty port for valid read request operation regardless of the

target device.

eccstatus

(7)

Output No A 2-bit wide error correction status port. Indicate whether the data

that is read from the memory has an error in single-bit with

correction, fatal error with no correction, or no error bit occurs.

•

00: No error

•

01: Illegal

•

10: A correctable error occurred and the error has been

corrected at the outputs; however, the memory array has not

been updated.

•

11:An uncorrectable error occurred and uncorrectable data

appears at the output.

This port is only available for Intel Arria

10 devices using M20K

memory block type.

(5)

Only applicable for the DCFIFO_MIXED_WIDTHS IP core.

(6)

Under certain condition, the SCFIFO asserts the empty signal without ever asserting the

almost_empty signal. Refer to SCFIFO ALMOST_EMPTY Functional Timing on page 12 for

more details.

(7)

Not applicable for the DCFIFO_MIXED_WIDTHS IP core.

SCFIFO and DCFIFO IP Cores User Guide

UG-MFNALT_FIFO | 2017.11.06

SCFIFO and DCFIFO IP Cores User Guide

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