TPS65981 USB Type-C和USB PD控制器

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"TI-TPS65981.pdf - Texas Instruments的USB Type-C和USB PD控制器" TI的TPS65981是一款高度集成的集成电路，专门设计用于管理USB Type-C连接器和USB Power Delivery (PD)协议。这款芯片在USB生态系统中扮演着重要的角色，提供电源管理、信号路由以及协议处理功能。 1. USB PD控制器: TPS65981包含了USB PD控制器，能够支持供电器件（Host）、受电器件（Device）和供电-受电器件（Dual Role Device）三种操作模式。它实现了双相标记编码/解码（BMC）物理层协议，确保数据传输的高效和稳定。此外，芯片内置的策略引擎可以根据预设规则来决定如何供电和接收电力，灵活适应不同的设备需求。该控制器还能够配置为自举控制或主机控制模式，以适应不同应用场景。 2. USB Type-C规范兼容性: TPS65981完全符合USB Type-C规范，具备以下功能： - 连接状态检测：可以检测USB电缆是否已连接。 - 电缆方向和角色检测：自动识别设备是作为主机还是设备，并相应地配置端口。 - CC和VCONN引脚管理：根据USB Type-C规范分配CC引脚，用于通信和确定连接状态；同时管理VCONN电源，为USB附件供电。 - 电流配置：支持默认的500mA、1.5A或3A三种电流等级，以适应不同设备的功率需求。 3. 端口电源开关: TPS65981集成了5V/3A的电源开关，可以安全地控制VBUS的通断，为Type-C连接的设备提供电源。这个开关设计允许高效地管理能量流，同时保护电路免受过载的影响。 4. 高速多路复用器: 该芯片还包括高速多路复用器，能够处理USB 2.0和高速数据（如SuperSpeed USB）信号，实现数据和电源的高效传输。这些复用器可以根据连接的设备类型和USB通信速度自动调整，确保最佳的信号质量。 5. 其他特点: TPS65981还提供了其他关键功能，如SBU1/2接口，用于支持USB Type-C的侧带使用（Sideband Use）数据线，以及支持从3.3V到20V的电压范围，能够适应广泛的电源输入条件。 TPS65981是一款针对USB Type-C连接和USB PD协议优化的解决方案，适用于需要高灵活性和智能电源管理的现代电子设备，如智能手机、平板电脑、笔记本电脑等。其强大的功能和全面的特性使得系统设计者能够轻松地实现符合最新USB标准的接口。

TPS65981

ZHCSFF4B –FEBRUARY 2016–REVISED AUGUST 2016

www.ti.com.cn

Port Power Switch Characteristics (continued)

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted. The maximum capacitance on VBUS,

when configured as a source, must not exceed 12 µF.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISS Soft-start charging current 5.5 7 8.5 μA

RSS_DIS Soft-start discharge resistance 0.6 1 1.4 kΩ

VTHSS Soft-start complete threshold 1.35 1.5 1.65 V

TSSDONE Soft-start complete time CSS = 220 nF 31.9 46.2 60.5 ms

VREVPHV

Reverse current blocking voltage threshold for

PP_HV switch

2 6 10 mV

VREVPEXT

Reverse current blocking voltage Threshold for

PP_EXT external switches

2 6 10 mV

VREV5V0

Reverse current blocking voltage threshold for

PP_5V0 switches

2 6 10 mV

VHVDISPD

Voltage threshold above VIN at which the pull-

down RHVDISPD on VBUS will disable during

a transition from PHV to 5V0

45 200 250 mV

VSAFE0V

Voltage that is a safe 0 V per USB-PD

Specifications

0 0.8 V

TSAFE0V Voltage transition time to VSAFE0V 650 ms

VSO_HV

Voltage on PP_HV or PP_HVEXT above which

the PP_HV or PP_EXT to PP_5V0 transition on

VBUS will meet transition requirements

9.9 V

SRPOS

Maximum slew rate for positive voltage

transitions

0.03 V/μs

SRNEG

Maximum slew rate for negative voltage

transitions

–0.03 V/μs

TSTABLE

EN to stable time for both positive and negative

voltage transitions

275 ms

VSRCVALID

Supply output tolerance beyond VSRCNEW

during time TSTABLE

–0.5 0.5 V

VSRCNEW Supply output tolerance –5 5 %

(1) All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum

difference between the two switches in a pair. ROND does not add to RON.

7.12 Port Data Multiplexer Switching Characteristics

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SWD MULTIPLEXER PATH

(1)

SWD_RON_U

On resistance of SWD_DATA/CLK to

C_USB_TP/TN/BP/BN

= 3.3 V, I

= 20 mA 35 55

= 1 V, I

= 20 mA 30 46

SWD_ROND_U

On resistance difference between P and N paths of

SWD_DATA/CLK to C_USB_ TP/TN/BP/BN

= 1 V to 3.3 V, I

= 20 mA –2.5 2.5 Ω

SWD_RON_S On resistance of SWD_DATA/CLK to C_SBU1/2

= 3.3 V, I

= 20 mA 26 42

= = 1 V, I

= 20 mA 24 37

SWD_ROND_S

On resistance difference between P and N paths of

SWD_DATA/CLK to C_SBU1/2

= 1 V to 3.3 V, I

= 20 mA –1.5 1.5 Ω

SWD_TON Switch-on time from enable of SWD path

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge-

pump steady state

SWD_TOFF Switch-off time from disable of SWD path

Time from disable bit at charge-

pump steady state

500 ns

SWD_BW 3-dB bandwidth of SWD path C

= 10 pF 200 MHz

DEBUG1 MULTIPLEXER PATH

DB1_RON_U On resistance DEBUG1 to C_USB_TP/BP

= 3.3 V, I

= 20 mA 14 26

= 1 V, I

= 20 mA 10 17

DB1_RON_S On resistance of DEBUG1 to C_SBU1

= 3.3 V, I

= 20 mA 9.5 17

= 1 V, I

= 20 mA 6.5 12

TPS65981

www.ti.com.cn

ZHCSFF4B –FEBRUARY 2016–REVISED AUGUST 2016

Port Data Multiplexer Switching Characteristics (continued)

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) See Port Data Multiplexer USB Endpoint Requirements and Characteristics for the USB_EP specifications.

DB1_TON Switch-on time from enable of DEBUG path

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge-

pump steady state

DB1_TOFF Switch-off time from disable of DEBUG path

Time from disable bit at charge-

pump steady state

500 ns

DB1_BW 3-dB bandwidth of DEBUG path C

= 10 pF 200 MHz

AUX MULTIPLEXER PATH

(1)

AUX_RON On resistance of AUX_P/N to C_SBU1/2

= 3.3 V, I

= 20 mA 3.5 7

= 1 V, I

= 20 mA 2.5 5

AUX_ROND

On resistance difference between P and N paths of

AUX_P/N to C_SBU1/2

= 1 V to 3.3 V, I

= 20 mA –0.25 0.25 Ω

AUX_TON Switch-on time from enable of AUX_P/N to C_SBU1/2

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge-

pump steady state

AUX_TOFF Switch-off time from disable of AUX_P/N to C_SBU1/2

Time from disable bit at charge-

pump steady state

500 ns

AUX_BW 3-dB bandwidth of AUX_P/N to C_SBU1/2 path C

= 10 pF 200 MHz

USB_RP MULTIPLEXER PATH

(1)(2)

USB_RON On resistance of USB_RP to C_USB_TP/TN/BP/BN

= 3 V, I

= 20 mA 4.5 10

= 400 mV, I

= 20 mA 3 7

USB_ROND

On resistance difference between P and N paths of

USB_RP to C_USB_TP/TN/BP/BN

= 0.4 V to 3 V, I

= 20 mA –0.15 0.15 Ω

USB_TON Switch-on time from enable of USB USB_RP path

Time from enable bit with charge

pump off

150

µs

Time from enable bit at charge-

pump steady state

USB_TOFF Switch-off time from disable of USB_RP path

Time from disable bit at charge-

pump steady state

500 ns

USB_BW 3-dB bandwidth of USB_RP path C

= 10 pF 850 MHz

USB_ISO Off isolation of USB_RP path

= 50 Ω, V

= 800 mV, f = 240

MHz

–19 dB

USB_XTLK Channel to channel crosstalk of USB_RP path R

= 50 Ω, f = 240 MHz –26 dB

C_SBU1/2 OUTPUT

R_SBU_OPEN Resistance of the open C_SBU1/2 paths V

= 0 V to LDO_3V3 1 MΩ

R_USB_OPEN Resistance of the open C_USB_T/B/P/N paths V

= 0 V to LDO_3V3 1 MΩ

(1) The TCLMP_PRT time includes the time through the digital synchronizers. When the clock speed is reduced, the signal assertion time

may be longer.

7.13 Port Data Multiplexer Clamp Characteristics

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCLMP_IND Clamp voltage triggering indicator to digital core 3.8 3.95 4.1 V

ICLMP_IND Clamp current at VCLMP_IND 10 250 μA

TCLMP_PRT

(1)

Time from clamp current crossing ICLMP_IND to

interrupt signal assertion

I ≥ ICLMP_IND rising 0 4 μs

ICLMP USB_EP and USB_RP port clamp current

V = LDO_3V3 250 nA

V = VCLMP_IND + 500 mV 3.5 15 mA

TPS65981

ZHCSFF4B –FEBRUARY 2016–REVISED AUGUST 2016

www.ti.com.cn

7.14 Port Data Multiplexer SBU Detection Requirements

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIH_PORT Port-switch detect input-high voltage LDO_3V3 = 3.3 V 2. v

VIL_PORT Port-switch detect input-low voltage LDO_3V3 = 3.3 V 0.8 V

7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RPU05 500-Ω pull-up and pull-down resistance LDO_3V3 = 3.3 V 350 500 650 Ω

RTPU5 5-kΩ pull-up and pull-down resistance LDO_3V3 = 3.3 V 3.5 5 6.5 kΩ

RPU100 100-kΩ pull-up and pull-down resistance LDO_3V3 = 3.3 V 70 100 130 kΩ

(1) The USB Endpoint PHY is functional across the entire VIN_3V3 operating range, but parameter values are only verified by design for

VIN_3V3 ≥ 3.135 V

7.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TRANSMITTER

(1)

T_RISE_EP Rising transition time Low-speed (1.5 Mbps) data rate only 75 300 ns

T_FALL_EP Falling transition time Low-speed (1.5 Mbps) data rate only 75 300 ns

T_RRM_EP Rise and fall time matching Low-speed (1.5 Mbps) data rate only –20% 25%

V_XOVER_EP Output crossover voltage 1.3 2 V

RS_EP

Source resistance of driver including 2nd-stage port-

data multiplexer

34 Ω

DIFFERENTIAL RECEIVER

(1)

VOS_DIFF_EP Input offset –100 100 mV

VIN_CM_EP Common-mode range 0.8 2.5 V

RPU_EP D–bias resistance Receiving 1.425 1.575 kΩ

SINGLE ENDED RECEIVER

(1)

VTH_SE_EP Single ended threshold Signal rising and falling 0.8 2 V

VHYS_SE_EP Single ended threshold hysteresis Signal falling 200 mV

7.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DATA CONTACT DETECT

IDP_SRC DCD source current LDO_3V3 = 3.3 V 7 10 13 μA

RDM_DWN DCD pull-down resistance 14.25 20 24.8 kΩ

VLGC_HI Threshold for no connection

VC_USB_TP/BP ≥

VLGC_HILDO_3V3 = 3.3 V

LDO_3V3 = 3.3 V

2 V

VLGC_LO Threshold for connection

VC_USB_TP/BP ≤ VLGC_LO

LDO_3V3 = 3.3 V

0.8 V

PRIMARY AND SECONDARY DETECT

VDX_SRC Source voltage 0.55 0.6 0.65 V

VDX_RSRC

Total series resistance because of port data

multiplexer

VDX_SRC = 0.65 V 65 Ω

VDX_ILIM VDX_SRC current limit 250 400 μA

IDX_SNK Sink current VC_USB_TN/BN ≥ 250 mV 25 75 125 μA

TPS65981

www.ti.com.cn

ZHCSFF4B –FEBRUARY 2016–REVISED AUGUST 2016

7.18 Analog-to-Digital Converter (ADC) Characteristics

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RES_ADC ADC current 10 bits

F_ADC ADC clock frequency 1.477 1.5 1.523 MHz

T_ENA ADC enable time 42.14 43 43.86 μs

T_SAMPLEA ADC input sample time 10.5 10.67 10.9 μs

T_CONVERTA ADC conversion time 7.88 8 8.12 μs

T_INTA ADC interrupt time 1.31 1.33 1.45 μs

LSB Least significant bit 1.152 1.17 1.188 mV

DNL Differential non-linearity –0.65 0.65 LSB

INL Integral non-linearity –1.2 1.2 LSB

GAIN_ERR

Gain error (divider) –1.5% 1.5%

Gain error (no divider) –1 1

VOS_ERR Buffer offset error –10 10 mV

THERM_ACC Thermal sense accuracy –8 8 °C

THERM_GAIN Thermal slope 3.095 mV/°C

THERM_V0 Zero degree voltage 0.823 V

7.19 Input-Output (I/O) Requirements and Characteristics

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SPI

SPI_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V

SPI_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V

SPI_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V

SPI_ILKG Leakage current Output is Hi-Z, V

= 0 to LDO_3V3 –1 1 μA

SPI_VOH SPI output-high voltage

= –8 mA, LDO_3V3=3.3 V 2.9 V

= –15 mA, LDO_3V3=3.3 V 2.5

SPI_VOL SPI output-low voltage

= 10 mA 0.4 V

= 20 mA 0.8

SWDIO

SWDIO_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V

SWDIO_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V

SWDIO_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V

SWDIO_ILKG Leakage current Output is Hi-Z, V

= 0 to LDO_3V3 –1 1 μA

SWDIO_VOH Output high voltage

= –8 mA, LDO_3V3 = 3.3 V 2.9 V

= –15 mA, LDO_3V3 = 3.3 V 2.5

SWDIO_VOL Output low voltage

= 10 mA 0.4 V

= 20 mA 0.8

SWDIO_RPU Pull-up resistance 2.8 4 5.2 kΩ

SWDIO_TOS SWDIO output skew to falling edge SWDCLK –5 5 ns

SWDIO_TIS

Input setup time required between SWDIO and rising

edge of SWCLK

6 ns

SWDIO_TIH

Input hold time required between SWDIO and rising edge

of SWCLK

1 ns

SWDCLK

SWDCL_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V

SWDCL_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V

SWDCL_THI SWDIOCLK HIGH period 0.05 500 μs

SWDCL_TLO SWDIOCLK LOW period 0.05 500 μs

SWDCL_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V

TPS65981

ZHCSFF4B –FEBRUARY 2016–REVISED AUGUST 2016

www.ti.com.cn

Input-Output (I/O) Requirements and Characteristics (continued)

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(1) DEBUG_CTL1/2 do not have an internal pull-down resistance path.

SWDCL_RPU Pull-up resistance 2.8 4 5.2 kΩ

GPIO (GPIO0, GPIO2-8, DEBUG1, DEBUG_CTL1/2, MRESET, RESETZ, BUSPOWERZ)

GPIO_VIH High-level input voltage

LDO_3V3 = 3.3 V 2 V

VDDDIO = 1.8 V 1.25

GPIO_VIL Low-level input voltage

LDO_3V3 = 3.3 V 0.8

VDDIO = 1.8 V 0.63

GPIO_HYS Input hysteresis voltage

LDO_3V3 = 3.3 V 0.2

VDDIO = 1.8 V 0.09

GPIO_ILKG I/O leakage current

Pin is Hi-Z;

= 0 V to VDD (VDDIO or

LDO_3V3)

–1 1 μA

GPIO_RPU

Pull-up resistance (GPIO0, GPIO2-8, DEBUG1,

MRESET, RESETZ, BUSPOWERZ)

Pull-up enabled

50 100 150

kΩ

Pull-up resistance (DEBUG_CTL1/2) 2.5 5 7.5

GPIO_RPD

Pull-down resistance (GPIO0, GPIO2-8, DEBUG1,

MRESET, RESETZ, BUSPOWERZ)

(1)

Pull-down enabled 50 100 150 kΩ

GPIO_DG Digital input path de-glitch 20 ns

GPIO_VOH GPIO output-high voltage

= –2 mA, LDO_3V3 = 3.3 V 2.9

= –2 mA, VDDIO = 1.8 V 1.35

GPIO_VOL GPIO output-low voltage

= 2 mA, LDO_3V3 = 3.3 V 0.4

= 2 mA, VDDIO = 1.8 V 0.45

I2C_IRQZ

OD_VOL Low-level output voltage I

= 2 mA 0.4 V

OD_LKG Leakage current Output is Hi-Z, V

= 0 to LDO_3V3 –1 1 μA

SBU

SBU_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V

SBU_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V

SBU_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V

7.20 I

C Slave Requirements and Characteristics

Recommended operating conditions; T

= –40°C to +105°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SDA AND SCL COMMON CHARACTERISTICS

ILEAK Input leakage current Voltage on Pin = LDO_3V3 -3 3 μA

VOL SDA output low voltage

IOL = 3 mA, LDO_3V3 = 3.3 V 0.4

IOL = 3 mA, VDDIO = 1.8 V 0.36

IOL SDA max output low current

VOL = 0.4 V 3

VOL = 0.6 V 6

VIL Input low signal

LDO_3V3 = 3.3 V 0.99

VDDIO = 1.8 V 0.54

VIH Input high signal

LDO_3V3 = 3.3 V 2.31

VDDIO = 1.8 V 1.26

VHYS Input Hysteresis

LDO_3V3 = 3.3 V 0.17

VDDIO = 1.8 V 0.09

TSP

C pulse width suppressed

50 ns

CI Pin Capacitance 10 pF

SDA AND SCL STANDARD MODE CHARACTERISTICS

FSCL

C clock frequency

0 100 kHz

THIGH

C clock high time

4 μs

剩余100页未读，继续阅读

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