摘要
本文是在理解伽罗瓦域乘法器工作原理的基础上,设计一个伽罗瓦域乘法器,并通过
verilog 硬件描述语言,用 Modelsim,Synplify 软件对其进行仿真,综合。
关键词:伽罗瓦域 乘法器 Verilog 仿真 综合
Abstract
This arcle is in understanding the working principle of Galois eld mulplier based on the design
of a Galois eld mulplier, and through the verilog hardware descriponlanguage, with
Modelsim, Synplify so!ware from simulaon, synthesis.
Key words: Galois Field Mulplier Simulaon synthesis
目录
摘
要 ........................................................................................................................................................
.................. 1
Abstract...............................................................................................................................................
.................. 2
正
文 ........................................................................................................................................................
.................. 4
一 、 课 题 及 设 计 要
求..................................................................................................................................... 4
a ) 课 题 内
容..................................................................................................................................................... 4
b ) 设 计 要
求..................................................................................................................................................... 4
二 、 伽 罗 瓦 域 背 景 介
绍............................................................................................................................... 4
a ) 域 和 伽 罗 瓦
域........................................................................................................................................... 4
b ) 伽 罗 瓦 域 两 种 操 作 — — 加 法 与 乘
法............................................................................................. 4
三 、 算 法 描
述..................................................................................................................................................... 4
四 、 设 计 过
程..................................................................................................................................................... 6
a ) 过 程 描
述..................................................................................................................................................... 6
b ) 程 序 流 程
图............................................................................................................................................... 7
五 、 verilog 源 代
码........................................................................................................................................ 8
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