Date Printed: April 6, 2004 Page 1
Overview of the
SPARC Architecture
Harry Porter
Computer Science Department
Portland State University
Abstract
This document provides an overview of the SPARC architecture and instruction set.
Only a portion of the architecture is covered. The view presented here is simplified
to provide an abstraction that should be adequate for user-level programming.
Memory
Main memory is byte addressable. Addresses are 4 bytes (i.e., 32 bits), allowing for up to 4
gigabytes of memory to be addressed.
Every instruction is 4 bytes (i.e., 32 bits) long. Instructions must be word aligned. That is, the their
addresses must be divisible by 4.
Bytes, Halfwords, Words, and Doublewords
Data is manipulated in 1, 2, 4, and 8 byte units called bytes, halfwords, words, and doublewords.
number number required aligned address
of bytes of bits alignment in binary
byte 1 8 none (any)
half 2 16 2 -----------0
word 4 32 4 ----------00
double 8 64 8 ---------000
剩余39页未读，继续阅读
评论0