200b_z01m_sdp_ddp_qdp_mobile_lpddr4.pdf_LPDDR的bank地址映射方法

LPDDR4

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Mobile LPDDR4 SDRAM

MT53B256M32D1, MT53B512M32D2, MT53B1024M32D4

Features

• Ultra-low-voltage core and I/O power supplies

–V

DD1

= 1.70–1.95V; 1.8V nominal

–V

DD2

DDQ

= 1.06–1.17V; 1.10V nominal

• Frequency range

– 1866–10 MHz (data rate range: 3733–20 Mb/s/

pin)

•16n prefetch DDR architecture

• 2-channel partitioned architecture for low RD/WR

energy and low average latency

• 8 internal banks per channel for concurrent opera-

tion

• Single-data-rate CMD/ADR entry

• Bidirectional/differential data strobe per byte lane

• Programmable READ and WRITE latencies (RL/WL)

• Programmable and on-the-fly burst lengths (BL =

16, 32)

• Directed per-bank refresh for concurrent bank op-

eration and ease of command scheduling

• Up to 15.0 GB/s per die (2 channels x 7.5 GB/s)

• On-chip temperature sensor to control self refresh

rate

• Partial-array self refresh (PASR)

• Selectable output drive strength (DS)

• Clock-stop capability

• RoHS-compliant, “green” packaging

• Programmable V

(ODT) termination

Options Marking

•V

DD1

DD2

: 1.8V/1.1V B

• Array configuration

– 256 Meg x 32 (2 channels x16 I/O) 256M32

– 512 Meg x 32 (2 channels x16 I/O) 512M32

– 1024 Meg x 32 (2 channels x8 I/O x 2) 1024M32

• Device configuration

– 256M16 x 2 channel x 1 die D1

– 256M16 x 2 channel x 2 die D2

– 512M8 x 2 channel x 4 die D4

• FBGA “green” package

– 200-ball WFBGA (10mm x 14.5mm x

0.80mm)

– 200-ball VFBGA (10mm x 14.5mm x

0.95mm)

• Speed grade, cycle time

– 535ps @ RL = 32/36 (x16 device) -053

– 625ps @ RL = 28/32 (x16 device),

32/36 (x8 device)

-062

• Operating temperature range

– –30°C to +85°C WT

• Revision :C

Table 1: Key Timing Parameters

Speed

Grade

Array

configura-

tion

Device

Type

Clock Rate

(MHz)

Data Rate

(Mb/s/pin)

WRITE Latency READ Latency

Set A Set B

DBI

Disabled

DBI

Enabled

-053 256Mb x 32,

512Mb x 32

x16 device 1866 3733 16 30 32 36

-062 256Mb x 32,

512Mb x 32

x16 device 1600 3200 14 26 28 32

1024Mb x 32 x8 device 1600 3200 14 26 32 36

Micron Confidential and Proprietary

200b: x32 Mobile LPDDR4 SDRAM

Features

09005aef8653a92d

200b_z01m_sdp_ddp_qdp_mobile_lpddr4.pdf – Rev. E 1/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Contents

General Description ....................................................................................................................................... 17

General Notes ............................................................................................................................................ 17

Package Block Diagrams ................................................................................................................................. 18

Ball Assignments and Descriptions ................................................................................................................. 21

Package Dimensions ....................................................................................................................................... 24

MR0, MR[6:3], MR8, MR13 Definition .............................................................................................................. 26

Parameters ............................................................................................................................................... 27

Functional Description ................................................................................................................................... 29

Monolithic Device Addressing ......................................................................................................................... 29

Simplified Bus Interface State Diagram ............................................................................................................ 33

Power-Up and Initialization ............................................................................................................................ 34

Voltage Ramp ............................................................................................................................................. 35

Reset Initialization with Stable Power .......................................................................................................... 37

Power-Off Sequence ....................................................................................................................................... 38

Controlled Power-Off .................................................................................................................................. 38

Uncontrolled Power-Off .............................................................................................................................. 38

Mode Registers ............................................................................................................................................... 39

Mode Register Assignments and Definitions ................................................................................................ 39

Commands and Timing .................................................................................................................................. 65

Truth Tables ................................................................................................................................................... 65

ACTIVATE Command ..................................................................................................................................... 68

Read and Write Access Modes ......................................................................................................................... 69

Preamble and Postamble ................................................................................................................................ 70

Burst READ Operation .................................................................................................................................... 73

Read Timing ............................................................................................................................................... 75

LZ(DQS),

LZ(DQ),

HZ(DQS),

HZ(DQ) Calculation ..................................................................................... 75

LZ(DQS) and

HZ(DQS) Calculation for ATE (Automatic Test Equipment) .................................................... 76

LZ(DQ) and

HZ(DQ) Calculation for ATE (Automatic Test Equipment) ........................................................ 77

Burst WRITE Operation .................................................................................................................................. 79

Write Timing .............................................................................................................................................. 81

WPRE Calculation for ATE (Automatic Test Equipment) .............................................................................. 82

WPST Calculation for ATE (Automatic Test Equipment) ............................................................................... 82

MASK WRITE Operation ................................................................................................................................. 83

Mask Write Timing Constraints for BL16 ...................................................................................................... 85

Data Mask and Data Bus Inversion (DBI [DC]) Function ................................................................................... 87

Preamble and Postamble Behavior .................................................................................................................. 91

Preamble, Postamble Behavior in READ-to-READ Operations ...................................................................... 91

READ to READ Operations – Seamless ......................................................................................................... 91

READ to READ Operations – Consecutive .................................................................................................... 92

WRITE to WRITE Operations – Seamless ...................................................................................................... 99

WRITE to WRITE Operations – Consecutive ................................................................................................ 102

PRECHARGE Operation ................................................................................................................................. 106

Burst READ Operation Followed by Precharge ............................................................................................ 106

Burst WRITE Followed by Precharge ........................................................................................................... 107

Auto Precharge .............................................................................................................................................. 108

Burst READ with Auto Precharge ................................................................................................................ 108

Burst WRITE with Auto Precharge .............................................................................................................. 109

RAS Lock Function .................................................................................................................................... 113

Delay time from WRITE to READ with Auto Precharge ................................................................................. 114

REFRESH Command ..................................................................................................................................... 115

Micron Confidential and Proprietary

200b: x32 Mobile LPDDR4 SDRAM

Features

09005aef8653a92d

200b_z01m_sdp_ddp_qdp_mobile_lpddr4.pdf – Rev. E 1/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Refresh Requirement ..................................................................................................................................... 120

SELF REFRESH Operation .............................................................................................................................. 121

Self Refresh Entry and Exit ......................................................................................................................... 121

Power-Down Entry and Exit During Self Refresh ......................................................................................... 122

Command Input Timing After Power-Down Exit ......................................................................................... 123

Self Refresh Abort ...................................................................................................................................... 124

MRR, MRW, MPC Command During

XSR,

RFC .......................................................................................... 124

Power-Down Mode ........................................................................................................................................ 127

Power-Down Entry and Exit ....................................................................................................................... 127

Input Clock Stop and Frequency Change ........................................................................................................ 137

Clock Frequency Change – CKE LOW ......................................................................................................... 137

Clock Stop – CKE LOW ............................................................................................................................... 137

Clock Frequency Change – CKE HIGH ........................................................................................................ 137

Clock Stop – CKE HIGH ............................................................................................................................. 138

MODE REGISTER READ Operation ................................................................................................................ 139

MRR after a READ and WRITE Command ................................................................................................... 140

MRR after Power-Down Exit ....................................................................................................................... 142

MODE REGISTER WRITE ............................................................................................................................... 143

Mode Register Write States ......................................................................................................................... 144

REF

Current Generator (VRCG) ..................................................................................................................... 145

REF

Training ................................................................................................................................................. 147

REF(CA)

Training ........................................................................................................................................ 147

REF(DQ)

Training ....................................................................................................................................... 152

Command Bus Training ................................................................................................................................. 157

Command Bus Training Mode .................................................................................................................... 157

Training Sequence for Single-Rank Systems ................................................................................................ 158

Training Sequence for Multiple-Rank Systems ............................................................................................ 159

Relation Between CA Input Pin and DQ Output Pin ..................................................................................... 160

Write Leveling ............................................................................................................................................... 164

Mode Register Write-WR Leveling Mode ..................................................................................................... 164

Write-Leveling Procedure .......................................................................................................................... 164

Input Clock Frequency Stop and Change .................................................................................................... 165

MULTIPURPOSE Operation ........................................................................................................................... 168

Read DQ Calibration Training ........................................................................................................................ 173

Read DQ Calibration Training Procedure .................................................................................................... 173

Read DQ Calibration Training Example ...................................................................................................... 175

MPC[READ DQ CALIBRATION] after Power-Down Exit ............................................................................... 176

Write Training ............................................................................................................................................... 177

Internal Interval Timer .............................................................................................................................. 182

DQS Interval Oscillator Matching Error ...................................................................................................... 184

OSC Count Readout Time .......................................................................................................................... 185

Thermal Offset .............................................................................................................................................. 187

Temperature Sensor ...................................................................................................................................... 187

ZQ Calibration ............................................................................................................................................... 188

ZQCAL Reset ............................................................................................................................................. 189

Multichannel Considerations ..................................................................................................................... 190

ZQ External Resistor, Tolerance, and Capacitive Loading ............................................................................. 191

Frequency Set Points ..................................................................................................................................... 192

Frequency Set Point Update Timing ........................................................................................................... 193

Pull-Up and Pull-Down Characteristics and Calibration .................................................................................. 197

On-Die Termination for the Command/Address Bus ....................................................................................... 198

ODT Mode Register and ODT State Table .................................................................................................... 198

Micron Confidential and Proprietary

200b: x32 Mobile LPDDR4 SDRAM

Features

09005aef8653a92d

200b_z01m_sdp_ddp_qdp_mobile_lpddr4.pdf – Rev. E 1/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.