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Cover

ASR3601

Datasheet

Communications Processor

Doc. No. ASR3601, Rev. A

CONFIDENTIAL

Document Classification: Proprietary Information

 
Table of Contents 
COVER  1 
DOCUMENT PURPOSE ............................................................................................................................................................... 3 
NUMBER REPRESENTATION ........................................................................................................................................................ 3 
PRODUCT  OVERVIEW .......................................................................................................................................................... 4 
NAMING CONVENTIONS .......................................................................................................................................................... 12 
1  INTRODUCTION ........................................................................................................................................... 14 
1.1
  SOC DEVICE FEATURES ............................................................................................................................................. 14 
2 FUNCTIONAL DESCRIPTION OVERVIEW .................................................................................................................. 18 
2.1
  ARCHITECTURE OVERVIEW ........................................................................................................................................ 18 
2.2
  CHIP CONFIGURATION .............................................................................................................................................. 20 
2.3
  MEMORY MAP ....................................................................................................................................................... 20 
2.4
  INTERRUPT CONNECTIVITY AND ASSIGNMENTS ............................................................................................................... 23 
2.5
  DMA CONNECTIVITY AND ASSIGNMENTS ...................................................................................................................... 31 
3 PIN MUXING AND MULTI-FUNCTION PINS .............................................................................................................. 38 
3.1
  FUNCTION ASSIGNMENTS FOR MULTIPLEXED I/O PINS .................................................................................................... 38 
3.2
  PINOUT ................................................................................................................................................................. 41 
3.3
  MULTIPLEXED SIGNAL FUNCTIONS .............................................................................................................................. 48 
3.4
  PAD-RING I/O DOMAINS POWER CONTROL .................................................................................................................. 54 
3.5
  PIN CONTROL UNIT ................................................................................................................................................. 58 
3.6
  FUNCTION ASSIGNMENTS FOR MULTI-FUNCTION I/O PINS.............................................................................................. 70 
3.7
  REGISTER DESCRIPTIONS ........................................................................................................................................... 72 
4 ARM CORTEX-R5 MODEM SUBSYSTEM ................................................................................................................... 73 
4.1
  OVERVIEW ............................................................................................................................................................. 73 
4.2
  FUNCTIONAL DESCRIPTION ........................................................................................................................................ 74 
4.3
   MEMORY MAP ...................................................................................................................................................... 76 
4.4
  INTERRUPT ............................................................................................................................................................. 76 
5 SQU ........................................................................................................................................................................ 77 
5.1
  OVERVIEW ............................................................................................................................................................. 77 
5.2
  FUNCTIONALITY ...................................................................................................................................................... 77 
6 PSRAM MEMORY CONTROLLER .............................................................................................................................. 79 
6.1
  INTRODUCTION ....................................................................................................................................................... 79 
6.2
  FEATURE LIST ......................................................................................................................................................... 79 
6.3
  OVERVIEW ............................................................................................................................................................. 80 
6.4
  FUNCTIONAL DESCRIPTION ........................................................................................................................................ 81 
7 SD HOST CONTROLLER ............................................................................................................................................ 85 
7.1
  FEATURES .............................................................................................................................................................. 85 
7.2
  SIGNAL DESCRIPTIONS .............................................................................................................................................. 87 
7.3
  SD/MMC BUS PROTOCOL DESCRIPTION .................................................................................................................... 88 
7.4
  SPECIAL BUS TRANSACTIONS ..................................................................................................................................... 90 
7.5
  CARD DETECTION .................................................................................................................................................... 97 
7.6
  SPI MODE ............................................................................................................................................................. 97 
7.7
  MMC MODE ......................................................................................................................................................... 97 
7.8
  CE-ATA MODE ...................................................................................................................................................... 97 
7.9
  REGISTER DESCRIPTIONS ........................................................................................................................................... 97 