CascadeImagingRadarCaptureReferenceDesignUsingADASprocessor.pdf_tidep-01012

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Micron MT41K512M16

x16 8Gbit

Micron MT41K512M16

x16 8Gbit

TDA2x Host Processor (ABC)

OS and Application Memory

2Gbyte Total

2x Micron MT41K512M16

16Gbit, 2x(64 Meg x 16 x 8 banks)

Micron MT41K512M8

4Gbit, 1x(64 Meg x 8 x 8 banks)

ECC Memory

512Mbyte Total

VIN1A

CSI2.0 to VIN Bridge

Lattice LIF MD6000 &URVV/LQNŒ

FPGA #1

VIN2A

CSI2.0 to VIN Bridge

Lattice LIF MD6000 &URVV/LQNŒ

FPGA #2

VIN3A

Lattice LIF MD6000 &URVV/LQNŒ

FPGA #3

CSI2.0 to VIN Bridge

VIN4A

Lattice LIF MD6000 &URVV/LQNŒ

FPGA #4

CSI2.0 to VIN Bridge

DDR3-1066

32-Bit+ECC

EMIF1

DDR3-1066

32-Bit

EMIF2

OS and Application Memory

2Gbyte Total

2x Micron MT41K512M16

16Gbit (64 Meg x 16 x 8 banks)

Hirose FX23-120S-

0.5SV10

AWR1243 RF Board

Connectors

CSI2.0

AWR#1

CSI2.0

AWR#2

CSI2.0

AWR#3

CSI2.0

AWR#3

UART3 1:4 MUX

UART AWR#1

UART AWR#2

UART AWR#3

UART AWR#4

SPI1

SPI3

SPI AWR#1/4

SPI AWR#2/3

GPIO

SOP

ERROR

UART

USB Bridge

USB2.0

Mini

Connector

UART1

USB3.0

Device

Connector

USB3.0

Super-Speed

(5Gbps)

EMU Port/VOUT

60-Pin MIPI

Debug Header

1G Ethernet PHY

DP83867IRPAPR

RGMII

RJ-45

Magnetics

QSPI Flash, 133MHz, 1Gbit

(128M x 8)

Micron MT25QL01GBBB8ESF

QSPI

HDMI

Type-A

Connector

HDMI1.4a

PCIe m.2

Host Connector

PCIe 2.0

5Gbps

MicroSD Card

Connector

MMC1

GPIO

AWR_RESETS

2:1 MUX

VOUT 10GigE

Header

JTAG

EMU

VOUT

TIDUEQ8–June 2019

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Cascade Imaging Radar Capture Reference Design Using Jacinto™ ADAS

Processor

Design Guide: TIDEP-01017

Cascade Imaging Radar Capture Reference Design Using

Jacinto™ ADAS Processor

Description

This reference design provides a processing

foundation for a cascaded imaging radar system.

Cascade radar devices can support front, long-range

(LRR) beam-forming applications as well as corner-

and side-cascade radar and sensor fusion systems.

This reference design provides qualified developers

the design materials to create a functioning software

evaluation platform for developing and testing ADAS

applications. The design shortens the development

time of a base platform supporting multiple automotive

radar front end and antenna subsystems.

Resources

TIDEP-01017 Design Folder

TDA2SX Product Folder

VisionSDK Tool Folder

TIDEP-01012 Design Folder

ASK Our E2E™ Experts

Features

• Compatible with SVTronics AWRx CIR radar

antenna reference design

• 4 × Lattice CrossLink™ FPGA-based interfaces

(1 each, per AWRx)

• High-performance TDA2x device with 4 radar

processing SIMD accelerators (1 EVE per AWRx)

• Ethernet and PCIe connectivity for control and data

respectively

Applications

• Long-range radar

• Imaging radar

• Drive assist ECU

• Radar ECU

• Medium and short range radar

• ADAS domain controller

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other

important disclaimers and information.

System Description

www.ti.com

TIDUEQ8–June 2019

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Cascade Imaging Radar Capture Reference Design Using Jacinto™ ADAS

Processor

1 System Description

Autonomous control of a vehicle provides quality-of-life and safety benefits in addition to making the

relatively mundane act of driving safer and less difficult. The quality-of-life features include the ability of a

vehicle to park itself, or to determine whether a lane change is possible, and provide features like

automatic cruise control—where a vehicle maintains a constant distance with respect to the car ahead of

it, essentially, tracking the velocity of the car in front of it. Autonomous braking and collision avoidance are

safety features that prevent accidents caused by driver inattention. These features work by observing the

area in front of a car and alerting the ADAS subsystems if obstacles are observed that are likely to hit the

car. Implementing these technologies requires a variety of sensors to detect obstacles in the environment

and track their velocities and positions over time.

1.1 Key System Specifications

This reference design has two sets of specifications because the radar is used as a multi-mode radar.

MIMO is the first specification. TX beamforming (TXBF) is the second specification,

Table 1. Key System Specifications

RECOMMENDED OPERATING CONDITIONS MIN TYP MAX

Input voltage (V

) 6 V 12 V 24 V

1.2 Why Cascade Radar?

Frequency-modulated continuous-wave (FMCW) radars allow the accurate measurement of range and

relative velocity of obstacles and other vehicles; therefore, radars are useful for autonomous vehicular

applications (such as parking assist and lane change assist) and car safety applications (autonomous

breaking and collision avoidance). An important advantage of radars over camera and light-detection-and-

ranging (LIDAR)-based systems is that radars are relatively immune to environmental conditions (such as

the effects of rain, dust, and smoke). FMCW radars can work in complete darkness and also bright

daylight (radars are not affected by glare) because they transmit and receive electromagnetic waves.

When compared with ultrasound, radars typically have a much longer range and much faster time of

transit for their signals.

Despite the many advantages of radar technology, in many cases, automotive manufacturers today still

use camera sensors as the primary sensor technology used to make final safety decisions in the system.

The radar sensor is being used as the secondary sensor; meaning, the vehicle system receives the Radar

warning, but decides to take an action only upon the camera sensor verification. The main reason is

limitation in radar angular resolution. The radar sensors deployed today in most vehicles lack the ability to

distinguish between static objects with the same range and same relative velocity.

Today, a typical front radar sensor has about a 5-degree angular resolution that corresponds to the ability

of the sensor to distinguish between objects that are 8.5 m apart at 100 m. Objects that are closer than

8.5 m appear as one object. For example, a vehicle stopped in the right lane, might look like a shoulder

road street lamp for example, and therefore would be ignored by the safety system.

This is about to change with the introduction of the Imaging Radar solution from Texas Instruments (TI).

The TI Imaging Radar is a four-chip cascade solution, that acts like a single-chip sensor but achieves

20Log10(N

) SNR gain in TX beamforming mode and 360/(N*pi) angular resolution (N is the number of

virtual antennas in a MIMO configuration).

The TI Imaging Radar solution, we can distinguish between static objects 0.6 degrees apart with all

antennae placed in single dimension linearly, and reach a 350-m object detecting range(angular resolution

is dependent on the antenna configuration and the number of TX/RX antennae).

This performance enables TI Imaging Radar to become the primary sensor in the vehicle and enhance

safety across weather and visibility conditions by providing a high-resolution image for both static and

moving objects.

www.ti.com

System Overview

TIDUEQ8–June 2019

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Cascade Imaging Radar Capture Reference Design Using Jacinto™ ADAS

Processor

2.2 Design Considerations

2.2.1 Cascade Radar Host Board based on TDA2x Application Processor

This cascade radar host board reference design supports the TDA2x application processor. TI designed

the TDA2x System-on-Chip (SoC) as a highly-optimized and scalable family of devices to meet the

requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2x family enables broad

ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS

vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2x SoC enables sophisticated embedded vision technology in automobiles by broadest range of

ADAS applications including front camera, park assist, surround view and sensor fusion on a single

architecture

The TDA2x SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and

floating-point TMS320C66x digital signal processor (DSP) cores, Vision AccelerationPac, Arm

Cortex

A15 MPCore™ and dual Cortex-M4 processors. The integration of a video accelerator for decoding

multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering

virtual views, enable a 3D viewing experience. In addition, the TDA2x SoC also integrates a host of

peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view

systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs)

offloading the perception analytics functionality from the application processor while also reducing the

power footprint. The Vision AccelerationPac is optimized for perception processing with a 32-bit RISC core

for efficient program execution and a vector coprocessor for specialized perception processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor,

including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a

debugging interface for visibility into source code execution.

The TDA2x ADAS processor is qualified according to the AEC-Q100 standard.

2.2.2 Cascade Radar RF Board Based on AWR1243P Sensor

The Cascade Radar RF board is built around the AWR1243P device. The AWR1243P is an integrated

single-chip, frequency modulated continuous wave (FMCW) sensor capable of operation in the 76 to 81

GHz frequency band. Built with TI’s low-power, 45-nm RFCMOS processor and enabling unprecedented

levels of analog and digital integration, the AWR1243P achieves an extremely small form factor. The

device has four receivers and three transmitters with a closed-loop phase-locked loop (PLL) for precise

and linear chirp synthesis.

Each transmitter includes a programmable 6-bit phase shifter (5.625 degree step) to enable beamforming

applications. Each device also includes two 20-GHz local oscillator (LO) output and two 20-GHz LO input

paths for sharing the VCO output with neighboring devices. This enables a cost-effective, totally passive,

cascaded radar architecture.

The sensor includes a built-in self test (BIST) for RF calibration and safety monitoring. Based on complex

baseband architecture, the sensor device supports an IF bandwidth of 15 MHz with reconfigurable output

sampling rates in both complex and real sampling modes. Two separate ARM Cortex R4F based

processors run the TI provided the radar front-end, calibration, and host processor interface firmware

targeting ASIL-B compliance.

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