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PN553_Datasheet.pdf
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nxp PN553 NFC芯片资料 PN553是为移动设备和符合NFC标准的设备集成而设计的NFC控制器。
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1. Introduction
This data sheet describes PN553, NXP Semiconductors NFC controller. This data sheet
requires additional documents for functional chip description and design in. Refer to the
references listed in this document for full list of documentation provided by NXP.
2. General description
PN553 is an NFC controller designed for integration in mobile devices and devices
compliant with NFC standards (NFC Forum, NCI, EMVCo, ETSI/SCP).
PN553 is designed based on learnings from previous NXP NFC device generation to ease
the integration of NFC technology in mobile devices by providing:
•
A low PCB footprint and a reduced external Bill of Material
•
An optimized architecture for low-power consumption in different modes (Standby,
low-power polling loop)
•
A highly efficient integrated power management unit allowing direct supply from an
extended battery supply range (2.8 V to 5.5 V). Moreover, this power management
provides full flexibility to support the different configurations in the mobile devices
(screen ON, screen OFF, phone OFF)
•
Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide
more output power.
•
2 SWP pads for UICC connections with dedicated power supply lines
PN553 embeds a new generation RF contactless front-end supporting various
transmission modes according to NFCIP-1 and NFCIP-2, ISO/IEC14443, ISO/IEC 15693,
MIFARE and FeliCa specifications. This new contactless front-end design brings a major
performance step-up with on one hand a higher sensitivity and on the other hand the
capability to work in active load modulation communication enabling the support of small
antenna form factor. It also allows to provide a higher output power by supplying the
transmitter output stage from 2.7 V to 5.25 V.
•
Enhanced Dynamic LMA (DLMA) to optimize and to enhance load modulation
amplitude depending on external field strength. It allows higher range communication
distance in card mode.
•
Independent LMA phase adjustment by step of 5° for type A, B and F
•
Dynamic Power control which allows to make use of the maximum power in reader
mode without exceeding the maximum power allowed by the standard in 0 distance.
•
Improved card mode receiver sensitivity down to 20 mV(p-p)
PN553
Near Field Communication (NFC) controller
Rev. 3.0 — 19 January 2017
355530
Product data sheet
COMPANY CONFIDENTIAL
PN553 embeds a new generation RF co
PN553 embeds a new generation RF co
extended battery supply range (2.8 V to 5.5 V). Moreover, this power management
provides full flexibility to support the differ
provides full flexibility to support the differ
(screen ON, screen OFF, phone OFF)
(screen ON, screen OFF, phone OFF)
•
Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide
Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide
more output power.
more output power.
•
A low PCB footprint and a redu
A low PCB footprint and a redu
An optimized architecture for low-power
An optimized architecture for low-power
low-power polling loop)
low-power polling loop)
A highly efficient integrated power management unit allowing direct supply from an
A highly efficient integrated power management unit allowing direct supply from an
extended battery supply range (2.8 V to 5.5 V). Moreover, this power management
extended battery supply range (2.8 V to 5.5 V). Moreover, this power management
antenna form factor. It also allows to prov
transmitter output stage from 2.7 V to 5.25 V.
transmitter output stage from 2.7 V to 5.25 V.
technology in mobile
technology in mobile
A low PCB footprint and a redu
A low PCB footprint and a redu
An optimized architecture for low-power
An optimized architecture for low-power
low-power polling loop)
low-power polling loop)
A highly efficient integrated power management unit allowing direct supply from an
A highly efficient integrated power management unit allowing direct supply from an
extended battery supply range (2.8 V to 5.5 V). Moreover, this power management
extended battery supply range (2.8 V to 5.5 V). Moreover, this power management
provides full flexibility to support the differ
provides full flexibility to support the differ
(screen ON, screen OFF, phone OFF)
(screen ON, screen OFF, phone OFF)
Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide
Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide
more output power.
more output power.
2 SWP pads for UICC connections with dedicated power supply lines
2 SWP pads for UICC connections with dedicated power supply lines
PN553 embeds a new generation RF co
PN553 embeds a new generation RF co
transmission modes acco
transmission modes acco
MIFARE and FeliCa specifications. This new co
MIFARE and FeliCa specifications. This new co
performance step-up with on one hand a higher
performance step-up with on one hand a higher
capability to work in active load modulation
capability to work in active load modulation
antenna form factor. It also allows to prov
PN553 is designed based on learnings from previous NXP NFC device generation to ease
PN553 is designed based on learnings from previous NXP NFC device generation to ease
This data sheet describes PN553, NXP Semiconductors NFC controller. This data sheet
This data sheet describes PN553, NXP Semiconductors NFC controller. This data sheet
requires additional documents for functional chip description and design in. Refer to the
requires additional documents for functional chip description and design in. Refer to the
document for full list of documentation provided by NXP.
document for full list of documentation provided by NXP.
PN553 is an NFC controller designed for in
PN553 is an NFC controller designed for in
compliant with NFC standards (NFC
compliant with NFC standards (NFC
ion (NFC) controller
ion (NFC) controller
ion (NFC) controller
ion (NFC) controller
•
•
Dynamic Power control which allows to ma
mode without exceeding the maximum power allowed by the standard in 0 distance.
••
distance in card mode.
distance in card mode.
•
•
Independent LMA phase adjustment by step of 5° for type A, B and F
Independent LMA phase adjustment by step of 5° for type A, B and F
Improved card mode receiver sensitivity down to 20 mV(p-p)
Improved card mode receiver sensitivity down to 20 mV(p-p)
amplitude depending on external field streng
amplitude depending on external field streng
distance in card mode.
distance in card mode.
Independent LMA phase adjustment by step of 5° for type A, B and F
Independent LMA phase adjustment by step of 5° for type A, B and F
Dynamic Power control which allows to ma
Dynamic Power control which allows to ma
mode without exceeding the maximum power allowed by the standard in 0 distance.
mode without exceeding the maximum power allowed by the standard in 0 distance.
Improved card mode receiver sensitivity down to 20 mV(p-p)
amplitude depending on external field streng
amplitude depending on external field streng
rding to NFCIP-1 and NFCIP-2, ISO/IEC14443, ISO/IEC 15693,
rding to NFCIP-1 and NFCIP-2, ISO/IEC14443, ISO/IEC 15693,
MIFARE and FeliCa specifications. This new co
MIFARE and FeliCa specifications. This new co
performance step-up with on one hand a higher
performance step-up with on one hand a higher
capability to work in active load modulation
capability to work in active load modulation
antenna form factor. It also allows to prov
antenna form factor. It also allows to prov
transmitter output stage from 2.7 V to 5.25 V.
transmitter output stage from 2.7 V to 5.25 V.
Enhanced Dynamic LMA (DLMA) to optimize and to enhance load modulation
Enhanced Dynamic LMA (DLMA) to optimize and to enhance load modulation
2 SWP pads for UICC connections with dedicated power supply lines
2 SWP pads for UICC connections with dedicated power supply lines
PN553 embeds a new generation RF co
PN553 embeds a new generation RF co
ntactless front-end supporting various
ntactless front-end supporting various
PN553 is designed based on learnings from previous NXP NFC device generation to ease
devices by providing:
devices by providing:
ced external Bill of Material
ced external Bill of Material
consumption in different modes (Standby,
consumption in different modes (Standby,
A highly efficient integrated power management unit allowing direct supply from an
A highly efficient integrated power management unit allowing direct supply from an
extended battery supply range (2.8 V to 5.5 V). Moreover, this power management
extended battery supply range (2.8 V to 5.5 V). Moreover, this power management
provides full flexibility to support the differ
ent configurations in
ent configurations in
Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide
Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide
Dynamic Power control which allows to ma
Dynamic Power control which allows to ma
mode without exceeding the maximum power allowed by the standard in 0 distance.
mode without exceeding the maximum power allowed by the standard in 0 distance.
Improved card mode receiver sensitivity down to 20 mV(p-p)
Improved card mode receiver sensitivity down to 20 mV(p-p)
Dynamic Power control which allows to maDynamic Power control which allows to ma
Independent LMA phase adjustment by step of 5° for type A, B and F
Independent LMA phase adjustment by step of 5° for type A, B and F
transmitter output stage from 2.7 V to 5.25 V.
transmitter output stage from 2.7 V to 5.25 V.
Enhanced Dynamic LMA (DLMA) to optimize and to enhance load modulation
Enhanced Dynamic LMA (DLMA) to optimize and to enhance load modulation
amplitude depending on external field streng
amplitude depending on external field streng
transmitter output stage from 2.7 V to 5.25 V.
transmitter output stage from 2.7 V to 5.25 V.
ntactless front-end supporting various
rding to NFCIP-1 and NFCIP-2, ISO/IEC14443, ISO/IEC 15693,
rding to NFCIP-1 and NFCIP-2, ISO/IEC14443, ISO/IEC 15693,
MIFARE and FeliCa specifications. This new co
MIFARE and FeliCa specifications. This new co
ntactless front-end dentactless front-end de
performance step-up with on one hand a higher
performance step-up with on one hand a higher
sensitivity and on the other hand the
sensitivity and on the other hand the
performance step-up with on one hand a higher
performance step-up with on one hand a higher
capability to work in active load modulation
capability to work in active load modulation
communication enabling
communication enabling
antenna form factor. It also allows to prov
ide a higher output power by supplying the
ide a higher output power by supplying the
transmitter output stage from 2.7 V to 5.25 V.
ntactless front-end supporting various
ntactless front-end supporting various
Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide
Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide
2 SWP pads for UICC connections with dedicated power supply lines
2 SWP pads for UICC connections with dedicated power supply lines
ntactless front-end supporting various
ntactless front-end supporting various
ent configurations in
ent configurations in
requires additional documents for functional chip description and design in. Refer to the
document for full list of documentation provided by NXP.
document for full list of documentation provided by NXP.
tegration in mobile devices and devices
tegration in mobile devices and devices
Forum, NCI, EMVCo, ETSI/SCP).
Forum, NCI, EMVCo, ETSI/SCP).
PN553 is designed based on learnings from previous NXP NFC device generation to ease
PN553 is designed based on learnings from previous NXP NFC device generation to ease
devices by providing:
consumption in different modes (Standby,
consumption in different modes (Standby,
A highly efficient integrated power management unit allowing direct supply from an
A highly efficient integrated power management unit allowing direct supply from an
extended battery supply range (2.8 V to 5.5 V). Moreover, this power management
extended battery supply range (2.8 V to 5.5 V). Moreover, this power management
ent configurations in
ent configurations in

355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
COMPANY CONFIDENTIAL
Rev. 3.0 — 19 January 2017
355530 2 of 70
NXP Semiconductors
PN553
Near Field Communication (NFC) controller
•
Support of single ended receiver
•
1.3 W output transmitter power
PN553 provides an architecture supporting several secure element interfaces (2 SWP)
allowing a full flexibility for the support of SWP-based secure elements. It enables
dynamic multiple secure element management (AID routing table).
Supported transmission modes are listed in Figure 1. For contactless card functionality,
the PN553 can act autonomously if previously configured by the host in such a manner.
PICC functionality can be supported without phone being turned on.
3. Features and benefits
ARM Cortex-M0 microcontroller core
Code memory: 128 kB ROM, 28 kB EEPROM
Data memory: 8 kB SRAM, 4 kB EEPROM
Highly integrated demodulator and decoder
Buffered output drivers to connect an antenna with minimum number of external
components
Integrated RF level detector
Integrated Polling Loop for automatic device discovery
Integrated routing mechanism to support multiple NFC execution environments
RF protocols supported
ISO/IEC 14443A, ISO/IEC 14443B PICC mode designed according to EMVCo
PICC (see Ref. 15)
ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital
protocol T4T platform and ISO-DEP (see Ref. 1)
FeliCa PCD mode
MIFARE PCD encryption mechanism (MIFARE 1K/4K)
(1) According to ISO/IEC 18092 (Ecma 340) standard.
Fig 1. PN553 transmission modes
3. Features and benefits
3. Features and benefits
(1) According to ISO/IEC 18092 (Ecma 340) standard.
(1) According to ISO/IEC 18092 (Ecma 340) standard.
Fig 1. PN553 transmission modes
Fig 1. PN553 transmission modes
3. Features and benefits
3. Features and benefits
ARM Cortex-M0 microcontroller core
ARM Cortex-M0 microcontroller core
Code memory: 128 kB ROM, 28 kB EEPROM
(1) According to ISO/IEC 18092 (Ecma 340) standard.
(1) According to ISO/IEC 18092 (Ecma 340) standard.
Fig 1. PN553 transmission modes
Fig 1. PN553 transmission modes
dynamic multiple secure element management (AID routing table).
dynamic multiple secure element management (AID routing table).
Supported transmission modes are listed in
Supported transmission modes are listed in
the PN553 can act autonomously if previously configured by the host in such a manner.
the PN553 can act autonomously if previously configured by the host in such a manner.
ed without phone being turned on.
ed without phone being turned on.
several secure element interfaces (2 SWP)
several secure element interfaces (2 SWP)
SWP-based secure elements. It enables
SWP-based secure elements. It enables
Near Field Communication (NFC) controller
Near Field Communication (NFC) controller
RF protocols supported
Integrated Po
Integrated Po
Integrated routing mechanism to support multiple NFC execution environmentsIntegrated routing mechanism to support multiple NFC execution environments
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
protocol T4T platform and ISO-DEP (see
protocol T4T platform and ISO-DEP (see
FeliCa PCD mode
MIFARE PCD encryption mechanism (MIFARE 1K/4K)
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
MIFARE PCD encryption mechanism (MIFARE 1K/4K)
MIFARE PCD encryption mechanism (MIFARE 1K/4K)
PICC (see
Ref. 15
Ref. 15
ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital
ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital
protocol T4T platform and ISO-DEP (see
protocol T4T platform and ISO-DEP (see
FeliCa PCD mode
FeliCa PCD mode
Integrated RF level detector
Integrated RF level detector
lling Loop for automatic device discovery
lling Loop for automatic device discovery
Integrated routing mechanism to support multiple NFC execution environments
Integrated routing mechanism to support multiple NFC execution environments
RF protocols supported
RF protocols supported
ISO/IEC 14443A, ISO/IEC 14443B PICC
ISO/IEC 14443A, ISO/IEC 14443B PICC
Ref. 15
)
Integrated RF level detector
Integrated RF level detector
ARM Cortex-M0 microcontroller core
ARM Cortex-M0 microcontroller core
Code memory: 128 kB ROM, 28 kB EEPROM
Code memory: 128 kB ROM, 28 kB EEPROM
Data memory: 8 kB SRAM, 4 kB EEPROM
Data memory: 8 kB SRAM, 4 kB EEPROM
Highly integrated demodulator and decoder
Highly integrated demodulator and decoder
Buffered output drivers to connect an
Buffered output drivers to connect an
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
Rev. 3.0 — 19 January 2017
Rev. 3.0 — 19 January 2017
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
ISO/IEC 14443A, ISO/IEC 14443B PICC
ISO/IEC 14443A, ISO/IEC 14443B PICC
ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital
ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital
protocol T4T platform and ISO-DEP (see
protocol T4T platform and ISO-DEP (see
FeliCa PCD mode
FeliCa PCD mode
MIFARE PCD encryption mechanism (MIFARE 1K/4K)
MIFARE PCD encryption mechanism (MIFARE 1K/4K)
lling Loop for automatic device discovery
lling Loop for automatic device discovery
Integrated routing mechanism to support multiple NFC execution environments
Integrated routing mechanism to support multiple NFC execution environments
Buffered output drivers to connect an
Buffered output drivers to connect an
antenna with minimum number of external
antenna with minimum number of external
lling Loop for automatic device discovery
lling Loop for automatic device discovery
Highly integrated demodulator and decoderHighly integrated demodulator and decoder
Code memory: 128 kB ROM, 28 kB EEPROM
Code memory: 128 kB ROM, 28 kB EEPROM
Data memory: 8 kB SRAM, 4 kB EEPROM
Data memory: 8 kB SRAM, 4 kB EEPROM
Highly integrated demodulator and decoder
Highly integrated demodulator and decoder

355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
COMPANY CONFIDENTIAL
Rev. 3.0 — 19 January 2017
355530 3 of 70
NXP Semiconductors
PN553
Near Field Communication (NFC) controller
NFC Forum tags T1T, T2T, T3T, T4T and T5T (see Ref. 1)
NFCIP-1, NFCIP-2 protocol (see Ref. 9 and Ref. 11)
NFC Forum certification release 9 for P2P, reader and card mode
FeliCa PICC mode
MIFARE PICC mode
ISO/IEC 15693/ICODE VCD mode (see Ref. 10)
NFC forum compliant embedded T4T for NDEF short record
Supported host interfaces
NCI protocol interface according to NFC Forum standardization (see Ref. 2)
I
2
C-bus High-speed mode (see Ref. 4)
SPI-bus (see Ref. 5)
Supported Secure Element interfaces
HCI protocol interfaces according to ETSI/SCP standardization Release 12
2 Single Wire Protocol (SWP) interface according to ETSI/SCP standardization
Release 11 for SWP compliant secure element connection
Flexible clock supply concept to facilitate PN553 integration
Internal oscillator for 27.12 MHz crystal connection
Integrated PLL unit to make use of mobile device reference clock and facilitate
PN553 integration
Integrated power management unit
Direct connection to a mobile battery (2.3 V to 5.5 V voltage supply range)
2 power regulators to supply UICC in class B and class C
Support different low-power states configuration: Hard Power-Down state and
Standby state activated by firmware
Autonomous mode when host is shut down
Automatic wake-up via RF field, internal timer, host interfaces and SWP interfaces
Integrated non-volatile memory to store data and executable code for customization
Standards compliancy
NFC Forum Device Requirements v1.3
EMVCo 2.5 for PICC and for PCD mode
ETSI/SCP 102 613 and 102 622 for SWP/HCI (see Ref. 12 and Ref. 13)
4. Applications
Mobile devices
Portable equipment (Personal Digital Assistants, tablet, notebook, wearable)
Consumer devices
4. Applications
4. Applications
2 power regulators to supply
Support different low-power states configuration: Hard Power-Down state and
Support different low-power states configuration: Hard Power-Down state and
Standby state activated by firmware
Standby state activated by firmware
Automatic wake-up via RF fiel
Automatic wake-up via RF fiel
Internal oscillator for 27
Integrated PLL unit to make use of mob
Integrated PLL unit to make use of mob
PN553 integration
PN553 integration
Integrated power management unit
Integrated power management unit
Direct connection to a mobile battery (2.3 V to 5.5 V voltage supply range)
Direct connection to a mobile battery (2.3 V to 5.5 V voltage supply range)
2 power regulators to supply
4. Applications
4. Applications
Flexible clock supply concept
Flexible clock supply concept
Internal oscillator for 27
Internal oscillator for 27
Integrated PLL unit to make use of mob
Integrated PLL unit to make use of mob
PN553 integration
PN553 integration
Integrated power management unit
Integrated power management unit
Direct connection to a mobile battery (2.3 V to 5.5 V voltage supply range)
Direct connection to a mobile battery (2.3 V to 5.5 V voltage supply range)
2 power regulators to supply
2 power regulators to supply
Support different low-power states configuration: Hard Power-Down state and
Support different low-power states configuration: Hard Power-Down state and
Standby state activated by firmware
Standby state activated by firmware
Autonomous mode when host is shut down
Autonomous mode when host is shut down
Automatic wake-up via RF fiel
Automatic wake-up via RF fiel
Integrated non-volatile memory to store data and executable code for customization
Integrated non-volatile memory to store data and executable code for customization
Standards compliancy
Standards compliancy
NFC Forum Device Requirements v1.3
NFC Forum Device Requirements v1.3
EMVCo 2.5 for PICC and for PCD mode
EMVCo 2.5 for PICC and for PCD mode
ETSI/SCP 102 613 and 102 622 for SWP/HCI (see
Release 11 for SWP compliant secure element connection
Release 11 for SWP compliant secure element connection
ISO/IEC 15693/ICODE VCD mode (see
ISO/IEC 15693/ICODE VCD mode (see
NFC forum compliant embedded T4T for NDEF short record
NFC forum compliant embedded T4T for NDEF short record
NCI protocol interface according to
NCI protocol interface according to
C-bus High-speed mode (see
C-bus High-speed mode (see
Ref. 4
Supported Secure Element interfaces
Supported Secure Element interfaces
HCI protocol interfaces according to
HCI protocol interfaces according to
2 Single Wire Protocol (SWP) interface
2 Single Wire Protocol (SWP) interface
NFC Forum tags T1T, T2T, T3T, T4T and T5T (see
NFC Forum tags T1T, T2T, T3T, T4T and T5T (see
Ref. 9
and
and
Ref. 11
NFC Forum certification release 9 for P2P, reader and card mode
NFC Forum certification release 9 for P2P, reader and card mode
Near Field Communication (NFC) controller
Near Field Communication (NFC) controller
Consumer devices
Consumer devices
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
Portable equipment (Personal Digital Assistants, tablet, notebook, wearable)
Portable equipment (Personal Digital Assistants, tablet, notebook, wearable)
Portable equipment (Personal Digital Assistants, tablet, notebook, wearable)
Portable equipment (Personal Digital Assistants, tablet, notebook, wearable)
NFC Forum Device Requirements v1.3
NFC Forum Device Requirements v1.3
EMVCo 2.5 for PICC and for PCD mode
EMVCo 2.5 for PICC and for PCD mode
ETSI/SCP 102 613 and 102 622 for SWP/HCI (see
ETSI/SCP 102 613 and 102 622 for SWP/HCI (see
d, internal timer, host interfaces and SWP interfaces
d, internal timer, host interfaces and SWP interfaces
Integrated non-volatile memory to store data and executable code for customization
Integrated non-volatile memory to store data and executable code for customization
553 integration
553 integration
.12 MHz crystal connection
.12 MHz crystal connection
ile device reference
ile device reference
Direct connection to a mobile battery (2.3 V to 5.5 V voltage supply range)
Direct connection to a mobile battery (2.3 V to 5.5 V voltage supply range)
UICC in class B and class C
UICC in class B and class C
Support different low-power states configuration: Hard Power-Down state and
Support different low-power states configuration: Hard Power-Down state and
Standby state activated by firmware
Autonomous mode when host is shut down
Autonomous mode when host is shut down
d, internal timer, host interfaces and SWP interfaces
d, internal timer, host interfaces and SWP interfaces
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
Rev. 3.0 — 19 January 2017
Rev. 3.0 — 19 January 2017
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
Portable equipment (Personal Digital Assistants, tablet, notebook, wearable)
Portable equipment (Personal Digital Assistants, tablet, notebook, wearable)
NFC Forum Device Requirements v1.3
NFC Forum Device Requirements v1.3
EMVCo 2.5 for PICC and for PCD mode
EMVCo 2.5 for PICC and for PCD mode
ETSI/SCP 102 613 and 102 622 for SWP/HCI (see
ETSI/SCP 102 613 and 102 622 for SWP/HCI (see
d, internal timer, host interfaces and SWP interfaces
d, internal timer, host interfaces and SWP interfaces
Integrated non-volatile memory to store data and executable code for customization
Integrated non-volatile memory to store data and executable code for customization
Support different low-power states configuration: Hard Power-Down state and Support different low-power states configuration: Hard Power-Down state and
NFC Forum standardization (see
Ref. 2
Ref. 2
)
ETSI/SCP standardization Release 12
ETSI/SCP standardization Release 12
according to ETSI/SCP standardization
according to ETSI/SCP standardization
ile device reference
ile device reference
clock and facilitate
clock and facilitate
Direct connection to a mobile battery (2.3 V to 5.5 V voltage supply range)
Direct connection to a mobile battery (2.3 V to 5.5 V voltage supply range)
UICC in class B and class C
UICC in class B and class C
Support different low-power states configuration: Hard Power-Down state and

355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
COMPANY CONFIDENTIAL
Rev. 3.0 — 19 January 2017
355530 4 of 70
NXP Semiconductors
PN553
Near Field Communication (NFC) controller
5. Quick reference data
[1] V
SS
represents V
SS(PAD)
and V
SS(TX)
.
[2] With X = 1 or 2.
[3] External clock on NFC_CLK_XTAL1 must be LOW.
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
V
BAT
battery supply voltage Card Emulation and Passive
Target; V
DD(UP)
> 2.9 V;
V
SS
= 0 V
[1]
2.5 - 5.5 V
Reader, Active Initiator and
Active Target;
V
DD(UP)
> 3.1 V; V
SS
= 0 V
[1]
2.8 - 5.5 V
V
DD(UP)
V
DD(UP)
input supply
voltage
Card Emulation and Passive
Target; V
SS
= 0 V
[1]
2.8 - 5.8 V
Reader, Active Initiator and
Active Target; V
SS
= 0 V
[1]
3.1 - 5.8 V
V
DD(PAD)
V
DD(PAD)
supply voltage supply voltage for host
interface; V
SS
= 0 V
[1]
1.65 1.8 1.95 V
V
DD(GPIO)
V
DD(GPIO)
supply voltage supply voltage for GPIO;
V
SS
= 0 V
[1]
1.65 1.8 1.95 V
V
DD(SIM_PM
U_X)
UICC power supply class C, UICC compliant to
ETSI 102 221 rel 9
[2]
1.65 - 1.98 V
class C, UICC compliant to
ETSI 102 221 rel 12;
I
VDD(SIM_PMU_X)
= 60 mA
[2]
1.75 - 1.85 V
class B;
I
VDD(SIM_PMU_X)
= 50mA
[2]
2.91 - 3.3 V
V
DD(SIM_X)
V
DD(SIM_X)
supply
voltage
no V
DD(SIM_PMU_X)
;
I
VDD(SIM_X)
= 10mA
[2]
1.625 - 1.98 V
I
BAT
battery supply current in Hard Power Down state;
V
BAT
= 3.6 V; T = 25 °C
[3]
- 10.5 16 A
in Standby state; V
BAT
= 3.6 V
enhanced RF detector - 32 52 A
low sensitivity RF detector - 21 36 A
in low-power polling loop;
V
BAT
= 3.6 V; T = 25 °C;
loop time = 500 ms
- 100 - A
continuous total current
consumption in PCD mode at
V
BAT
= 3.6 V
[4]
- - 290 mA
I
th(Ilim)
current limit threshold current limiter on transmitter
[4]
270 300 330 mA
P
tot
total power dissipation PCD mode at typical
V
DD(TX)
= 5.25 V,
V
DD(UP)
= 5.8 V and
V
BAT
= 3.6 V; includes power
from V
BAT
and V
DD(UP)
- - 620 mW
T
amb
ambient temperature JEDEC PCB-0.5 25 - +85 C
V
V
DD(SIM_X)DD(SIM_X)
I
I
BATBAT
DD(SIM_PM
UICC power supply class C, UICC compliant to
UICC power supply class C, UICC compliant to
battery supply current in Ha
battery supply current in Ha
V
V
DD(SIM_X)
DD(SIM_X)
voltage
voltage
UICC power supply class C, UICC compliant to
UICC power supply class C, UICC compliant to
supply voltage supply voltage for GPIO;
supply voltage supply voltage for host
supply voltage supply voltage for host
Card Emulation and Passive
Card Emulation and Passive
Target; V
Target; V
Reader, Active Initiator and
Reader, Active Initiator and
Reader, Active Initiator and
Reader, Active Initiator and
Active Target;
Active Target;
VV
DD(UP)
DD(UP)
battery supply voltage Card Emulation and Passive
battery supply voltage Card Emulation and Passive
Target; V
Target; V
DD(UP)
DD(UP)
SS
SS
= 0 V
= 0 V
Conditions
battery supply voltage Card Emulation and Passive
Near Field Communication (NFC) controller
Near Field Communication (NFC) controller
[1] V
[1] V
TT
amb
amb
tot
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
[1] V
[1] V
SS
SS
represents V represents V
[2] With X = 1 or 2.
[2] With X = 1 or 2.
[3] External clock on NFC_CLK_XTAL1 must be LOW.
[3] External clock on NFC_CLK_XTAL1 must be LOW.
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
[3] External clock on NFC_CLK_XTAL1 must be LOW.
represents V
represents V
SS(PAD)
SS(PAD)
[2] With X = 1 or 2.
[2] With X = 1 or 2.
[3] External clock on NFC_CLK_XTAL1 must be LOW.
[3] External clock on NFC_CLK_XTAL1 must be LOW.
ambient temperature JEDEC PCB-0.5
ambient temperature JEDEC PCB-0.5
ambient temperature JEDEC PCB-0.5
total power dissipation PCD mode at typical
total power dissipation PCD mode at typical
current limit threshold curr
current limit threshold curr
current limit threshold curr
current limit threshold curr
low sensitivity RF detector - 21 36
low sensitivity RF detector - 21 36
in low-power polling loop;
in low-power polling loop;
VV
BAT
BAT
loop time = 500 ms
loop time = 500 ms
continuous total current
enhanced RF detector - 32 52
enhanced RF detector - 32 52
in Standby state; V
in Standby state; V
= 3.6 V; T = 25 °C
= 3.6 V; T = 25 °C
rd Power Down state;
rd Power Down state;
DD(SIM_PMU_X)
DD(SIM_PMU_X)
VDD(SIM_X)
VDD(SIM_X)
= 10mA
= 10mA
VDD(SIM_PMU_X)
VDD(SIM_PMU_X)
= 50mA
= 50mA
class C, UICC compliant to
class C, UICC compliant to
ETSI 102 221 rel 12;
ETSI 102 221 rel 12;
VDD(SIM_PMU_X)
VDD(SIM_PMU_X)
= 60 mA
= 60 mA
UICC power supply class C, UICC compliant to
UICC power supply class C, UICC compliant to
ETSI 102 221 rel 9
supply voltage supply voltage for GPIO;
supply voltage supply voltage for GPIO;
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
Rev. 3.0 — 19 January 2017
Rev. 3.0 — 19 January 2017
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
and V
and V
SS(TX)
SS(TX)
[3] External clock on NFC_CLK_XTAL1 must be LOW.
[3] External clock on NFC_CLK_XTAL1 must be LOW.
ambient temperature JEDEC PCB-0.5
ambient temperature JEDEC PCB-0.5
from V
VV
total power dissipation PCD mode at typical total power dissipation PCD mode at typical
V
V
DD(TX)
DD(TX)
V
DD(UP)
total power dissipation PCD mode at typical
total power dissipation PCD mode at typical
current limit threshold curr
current limit threshold curr
ent limiter on transmitter
ent limiter on transmitter
continuous total current
continuous total current
consumption in PCD mode at
consumption in PCD mode at
V
BAT
BAT
= 3.6 V
= 3.6 V
continuous total current continuous total current
continuous total current
in low-power polling loop;
in low-power polling loop;
= 3.6 V; T = 25 °C;
= 3.6 V; T = 25 °C;
loop time = 500 ms
loop time = 500 ms
low sensitivity RF detector - 21 36
low sensitivity RF detector - 21 36
enhanced RF detector - 32 52
enhanced RF detector - 32 52
enhanced RF detector - 32 52enhanced RF detector - 32 52
in Standby state; V
in Standby state; V
BATBAT
rd Power Down state;
rd Power Down state;
= 3.6 V; T = 25 °C
= 3.6 V; T = 25 °C
= 10mA
class C, UICC compliant to
[2][2]
[2]
[2]
1.65 - 1.98 V1.65 - 1.98 V
1.65 1.8 1.95 V
1.65 1.8 1.95 V
1.65 1.8 1.95 V
1.65 1.8 1.95 V
3.1 - 5.8 V
3.1 - 5.8 V
2.8 - 5.8 V
2.8 - 5.8 V

355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
COMPANY CONFIDENTIAL
Rev. 3.0 — 19 January 2017
355530 5 of 70
NXP Semiconductors
PN553
Near Field Communication (NFC) controller
[4] This is considering an antenna tuned to sink maximum 250 mA continuous current from the transmitter. The
antenna shall be tuned to never exceed this 250 mA maximum current.
6. Ordering information
[1] x: correspond to features variant.
[2] y: 1 = I
2
C-bus interface; 2 = SPI-bus interface.
[3] zz: correspond to firmware variant.
7. Marking
Table 2. Ordering information
Type number Package
Name Description Version
PN553xyEV/C1zz
[1][2][3]
VFBGA64 plastic very thin fine-pitch ball grid array
package; 64balls
SOT1860-1
Fig 2. PN553 package marking (top view)
Fig 2. PN553 package marking (top view)
Fig 2. PN553 package marking (top view)
C-bus interface; 2 = SPI-bus interface.
C-bus interface; 2 = SPI-bus interface.
[3] zz: correspond to firmware variant.
[3] zz: correspond to firmware variant.
Description
VFBGA64 plastic very thin
VFBGA64 plastic very thin
package; 64balls
package; 64balls
m 250 mA continuous current from the transmitter. The
m 250 mA continuous current from the transmitter. The
antenna shall be tuned to never exceed this 250 mA maximum current.
antenna shall be tuned to never exceed this 250 mA maximum current.
Near Field Communication (NFC) controller
Near Field Communication (NFC) controller
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
Fig 2. PN553 package marking (top view)
Fig 2. PN553 package marking (top view)
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
Rev. 3.0 — 19 January 2017
Rev. 3.0 — 19 January 2017
355530 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights rese
Fig 2. PN553 package marking (top view)
Fig 2. PN553 package marking (top view)
SOT1860-1
SOT1860-1
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