AUX/Single Power Domain
System Power Supply
Platform I/O Hub
Baseboard Management
Controller
Networking Silicon
PORT 1
WAKE#
PWRBRK#
EP Bifurcation Control
Pin(s)
CLK_IN
ARB_OUT
CRS_DV
RXD[0:1]
TX_EN
TXD[0:1]
PACKAGE_ID[0] = SLOT_ID0
PACKAGE_ID[1] = SLOT_ID1
PACKAGE_ID[2] = 0b0
V
BUS
USB_DATp
V
BUS
Detection
PCIe [0:3]
PCIe [4:7]
PCIe [8:11]
PCIe [12:15]
REFCLK0 – EP0
REFCLK1 – EP1
REFCLK2 – EP2
REFCLK3 – EP3
PERST0 – EP0
PERST1 – EP1
PERST2 – EP2
PERST3 – EP3
4 x4 case: four REFCLKs
2 x8 case: two REFCLKs
1 x16 case: on e REFCLK
EP #0 – 1 x4EP #1 – 1 x4
EP #2 – 1 x4EP #3 – 1 x4
EP #0 - 1 x8EP #1 - 1 x8
EP #0 - 1 x16
Link 2
Link 3
Link 0
Link 1
Link 2
Link 3
Link 0
Link 1
OCP NIC 3.0 SFF - Single Host Implementation Example (single, dual, quad link) with a 1x16 Option C card
REFCLK0
REFCLK1
REFCLK2
REFCLK3
PERST0
PERST1
PERST2
PERST3
AUX_PWR_GOOD
(Internal)
WAKE_N
PWRBRK0#
Comb.
Gate
Logic
BIF0#
BIF1#
BIF2#
50MHz
Clock
RBT_CLK_IN
REF_CLK
CRS_DV
RXD[0:1]
TX_EN
TXD[0:1]
RBT_CRS_DV
RBT_RXD[0:1]
RBT_TX_EN
RBT_TXD[0:1]
RBT_ARB_OUT
RBT_ARB_IN
FET Switch
ARB_IN
BIF Pin Option (Static Configuration)
BIF0#
BIF1#
BIF2#
Comb.
Gate
Logic
AUX_PWR_EN
To power topo logy
Primary/Secondary
Connector
FRU EEPROM
“AUX Power Good” (local signal)
Isolator
SMCLK
SMDAT
A0
A1
A2
+3.3V (NIC)
SLOT_ID0 = 0
SLOT_ID1 = 0
See pin descr iptions for
SLOT_ID[1:0] en coding values.
SMCLK
SMDAT
SLOT_ID0
SLOT_ID1
+3.3V_EDGE
PRSNTB0#
PRSNTB1#
PRSNTB2#
PRSNTB3#
+3.3V_EDGE
SMRST*
To SMBus devic es with
RST* pin (e.g . I/O
Expander)
Optional MAIN Power Domain
SVR #1 SVR #2
PG PG
VINVIN
AUX_PWR_EN
SVR #3
PG
VIN
+3.3V_EDGE
10k
Ohm
+12V_EDGE
EN EN EN
SVR #4
PG
VIN
MAIN_PWR_EN
EN
Optional. Impl ementation dependent on en dpoint silicon.
VOUT VOUT VO UT
VOUT
100k
Ohm
+3.3V_EDGE
COMB.
Logic
10k
Ohm
Optional logic for
Programming
Mode
N-FET
Powered from
+3.3V_EDGE
MAIN_PWR_EN
AUX_PWR_EN
MAIN_PWR_EN
NIC_PWR_GOOD
RBT_ISOLATE#
+3.3V_
EDGE
Host PLD
DATA_OUT
CLK (12.5MH z)
74LV594 #0
QA
QB
QC
QD
QE
QF
QG
QH
QH’
VCC
SER
SRCLK
SRCLRn
RCLK
RCLRn
GND
74LV165 #0
A
B
C
D
E
F
G
H
SER
VCC
CLK
CLK_INH
SH/LDn
QH
QH’
GND
+3.3V_EDGE
LINK_SPDA_ P0#
LINK_SPDB_P0 #
ACT_P0#
LINK_SPDA_ P1#
LINK_SPDB_P1 #
ACT_P1#
LINK_SPDA_ P2#
LINK_SPDB_P2 #
DATA_IN
LD_N
74LV165 #1
A
B
C
D
E
F
G
H
SER
VCC
CLK
CLK_INH
SH/LDn
QH
QH’
GND
PRSNTB[0]# (Mirrored from Primary Conn ector)
PRSNTB[1]# (Mirrored from Primary Conn ector)
PRSNTB[2]# (Mirrored from Primary Conn ector)
PRSNTB[3]# (Mirrored from Primary Conn ector)
WAKE_N (Mirr ored from Primary Connect or)
74LV165 #2
A
B
C
D
E
F
G
H
SER
VCC
CLK
CLK_INH
SH/LDn
QH
QH’
GND
ACT_P2#
LINK_SPDA_ P3#
LINK_SPDB_P3 #
ACT_P3#
LINK_SPDA_ P4#
LINK_SPDB_P4 #
ACT_P4#
LINK_SPDA_ P5#
+3.3V_EDGE
1k
Ohm
1k
Ohm
+3.3V_EDGE
Inverter
+3.3V_EDGE
+3.3V_EDGE
74LV165 #3
A
B
C
D
E
F
G
H
SER
VCC
CLK
CLK_INH
SH/LDn
QH
QH’
GND
LINK_SPDB_P5 #
ACT_P5#
LINK_SPDA_ P6#
LINK_SPDB_P6 #
ACT_P6#
LINK_SPDA_ P7#
LINK_SPDB_P7 #
ACT_P7#
Implement a 1k Ohm pull up to 3.3Vaux
for the last shi ft register on the bus.
Implement a 1k Ohm pull up to 3.3Vaux
for the last shi ft register on the bus.
Implement a 1k Ohm pull up to 3.3Vaux
for the last shi ft register on the bus.
Optional depe nding on line side port co unt
10k
Ohm
+3.3V_EDGE
+3.3V_EDGE
1k
Ohm
+3.3V_EDGE
1k
Ohm
+3.3V_EDGE
Reserved future use
Reserved future use
Reserved future use
Reserved future use
Reserved future use
Reserved future use
Reserved future use
Reserved future use
1k
Ohm
DATA_OUT
CLK
DATA_IN
LD_N
BIF0#
BIF2#
BIF1#
PWRBRK0#
SMCLK
SMDAT
SMRST*
PRSNTB0#
PRSNTB1#
PRSNTB2#
PRSNTB3#
NIC_PWR_GOOD
Hot Swap Example (optional)
+12V_EDGE
Hotswap
Controller
VIN
EN
VOUT
+12V
Enable +12V_EDG E on non-zero
PRSNTB[3:0]# value.
PRSNTA#
1k
Ohm
PRSNTB0#
PRSNTB1#
PRSNTB2#
PRSNTB3#
+3.3V_EDGE
Tss
Css
Connector Boundary
To SVR inputs
PRSNTA#
PET[0:3]
PER[0:3]
PET[4:7]
PET[8:11]
PET[12:15]
PER[4:7]
PER[8:11]
PER[12:15]
+3.3V_EDGE
+3.3V_EDGE
4.7 - 10k
Ohm
95k
Ohm
USB_DATn
USB_DATp
USB_DATn
USB_DATp
USB_DATn
+5.0V (NIC)
+3.3V_EDGE
SMCLK
SMDAT
+12V_EDGE
+3.3V_EDGE
Note: REFCLK0 a nd PERST0 required for a ll OCP
NIC 3.0 cards. Leave REFCLK[1:3] and PERS T[1:3]
as N.C. if not im plemented
N.C. N.C.
RFU[1:2]
VCC
+3.3V_EDGE
+12V_EDGE
WP
+12V_EDGE
+3.3V_EDGE
TX
RX
SFP
TX
RX
GREEN
Refer to Sectio n 3.4.4 for details on arbitr ation.
FAN_ON_AUXTEMP_WARN _N TEMP_CRIT_N
Refer to section 3.4.3 for details on the
SMBus interface
Refer to section 3.4.2 for details on the
BIF Pin Usage. B IF implementations may
also be static (ex ample at right)
Refer to Sectio n 3.4.5 for details on the
Scan Chain
Refer to Sectio n 3.4.6, 3.8, for details on the power
supply pins, a nd power state machine req uirements.
Refer to Sectio n 3.11 for details on the power
sequence timin g requirements.
Refer to section 3.4.7 for details on the
USB 2.0 Interf ace
Refer to section 3.6 for details on PCIe
mapping
Refer to section s 2.2 and 3.7 for details
on line-side imp lementations, LEDs, and
port number ing
Single Host Root
Complex
(1 x16, 2 x8, or 4 x4)
PCIe [0:3]
PCIe [4:7]
PCIe [8:11]
PCIe [12:15]
Host 0
RC #0 - 1 x8RC #1 - 1 x8
RC #0 - 1 x16
RC #0 – 1 x4RC #1 – 1 x4RC #2 – 1 x4RC #3 – 1 x4
Platform
Reset
PCIe 1:4
Clock
Buffer
REFCLK0
REFCLK1
REFCLK2
REFCLK3
PERST0
PERST1
PERST2
PERST3
Refer to Sectio ns 3.4.4 and 4.8.1 for detai ls on
the NC-SI over RBT Package Addressing
requirements. PACKAGE_ID[2] == 0b0 for s ingle
device card implem entations.
Refer to Sectio n 3.9 for the power supply r ail
requirements for +12V_EDGE, +3.3V_EDGE and slot
power envelope s.
Refer to Sectio n 4.9.1 for the SMBus
Address Map a nd requirements for the
FRU EEPROM ad dressing.
FET
Switch
GREEN
Amber
LINK_SPDA_ P0#
LINK_SPDB_P0 #
ACT_P0#
PORT 2
TX
RX
SFP
TX
RX
GREEN
GREEN
Amber
LINK_SPDA_ P1#
LINK_SPDB_P1 #
ACT_P1#
PORT 3
TX
RX
SFP
TX
RX
GREEN
GREEN
Amber
LINK_SPDA_ P2#
LINK_SPDB_P2 #
ACT_P2#
PORT 4
TX
RX
SFP
TX
RX
GREEN
GREEN
Amber
LINK_SPDA_ P3#
LINK_SPDB_P3 #
ACT_P3#
Refer to Sectio n 3.4.2, and 3.5 for details o n
the PRSNTA #/PRSNTB[3:0]# implementatio n
10k
Ohm
WAKE_N
+3.3V_EDGE
PCIe Sub-System
NC-SI over RBT Sub-System
USB Sub-System
Line-Side I/O
1k
Ohm
Note: For baseb oard designs with multiple Primary
Connectors, co nnect ARB_IN and ARB_OUT to an analog mux
to complete the NC-SI HW arbitration ring based on the
number of cards installed on the NC-SI over RBT bus.
Command-based (so ftware) arbitration may o ptionally be
used for shared b us topologies. Refer to D SP0222 for details.
GND
Refer to Sectio n 4.10.2 for FRU EEPROM
Write Protecti on Mechanisms
SFF Primary
Connector
PWRBRK#
DATA_OUT shift register not implemented
in this version of the specification
Refer to Sectio n 3.10 for Hot Swap consi derations
and implemen tation strategies
“AUX Power Good”
“MAIN Powe r Good”
Thermal Monitoring
FRU EEPROM Implementation: Not write protected
FRU EEPROM
VCC
+3.3V_EDGE
FRU EEPROM Implementation: FRU always write protected
WP
FRU EEPROM
VCC
+3.3V_EDGE
WP
FRU EEPROM Implementation: WP controlled by mechanical jumper
or switch
FRU EEPROM
VCC
+3.3V_EDGE
WP
FRU EEPROM Implementation: WP controlled by network silicon GPIO
FRU EEPROM
VCC
+3.3V_EDGE
WP
Network
Silicon
GPIO
Refer to Sectio n 3.4.5 for Scan chain
thermal monit oring pin requirements
100 kOhm
100 kOhm
Refer to the PCIe Base Specification for t he
appropriate AC c oupling cap (C
TX
) value
associated with each PCIe generation.
+12V_EDGE
PRSNTB0#
PRSNTB1#
PRSNTB2#
PRSNTB3#
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