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3/9/2010 70LCX

Data Sheet

B50610

B50610-DS07-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 09/18/09

10/100/1000BASE-T Gigabit Ethernet Transceiver

Figure 1: Functional Block Diagram

GENERAL DESCRIPTION FEATURES

The Broadcom

B50610 is a triple-speed 1000BASE-T/

100BASE-TX/10BASE-T Gigabit Ethernet (GbE)

transceiver integrated into a single monolithic CMOS chip.

The device performs all physical-layer functions for

1000BASE-T, 100BASE-TX, and 10BASE-T Ethernet on

standard category 5 UTP cable. 10BASE-T can also run

on standard category 3, 4, and 5 UTP. The B50610 is a

highly integrated solution combining digital adaptive

equalizers, ADCs, phase-locked loops, line drivers,

encoders, decoders, echo cancellers, crosstalk

cancellers, and all required support circuitry. Based on

Broadcom’s proven Digital Signal Processor technology,

the B50610 is designed to be fully compliant with RGMII,

allowing compatibility with industry-standard Ethernet

MACs and switch controllers.

Designed for reliable operation over worst-case

category 5 cable, the B50610 automatically negotiates

with its link partner to determine the highest possible

operating speed. The device detects and corrects most

common wiring problems. The B50610 features

CableChecker™ diagnostics, which detects common

cable problems including shorts, opens, and cable length.

APPLICATIONS

• GbE switches and uplinks

• Single-chip integrated triple-speed Ethernet

transceiver

• 1000BASE-T IEEE 802.3ab

• 100BASE-TX IEEE 802.3u

• 10BASE-T IEEE 802.3™

• Supports only RGMII MAC interface

• Supports SOFT-RESET

• Ethernet@Wirespeed™

• Integrated voltage regulator

• Trace matched output impedance

• Lineside loopback

• Low EMI emissions

• Cable plant diagnostics

• Robust CESD tolerance

• Support for jumbo packets up to 10 KB

• Detection and correction of pair swaps

(MDI crossover), pair skew, and pair polarity

• Advanced power management

• IEEE 1149.1 (JTAG) boundary scan

• Super isolate mode

• 100-pin FBGA and 48-pin MLP packages

SYMBOL

ENCODER

SYMBOL

DECODER/

ALIGNER

XTALK

CANCELLER

DEF/

TRELLIS

DECODER

TIMING &

PHASE

RECOVERY

FFE

ECHO

CANCELLER

BASELINE

WANDER

CORRECTION

PGA

AUTO-

NEGOTIATION

CLOCK

GENERATOR

BIAS GENERATOR

VOLTAGE

REGULATOR

MII

REGISTERS

MII

MGMT

CONTROL

LED

DRIVERS

TXDAC

ADC

TXD[3:0]

TX_EN

GTX_CLK

RX_DV

RXC

CLK125

RXD[3:0]

LED2

LED3

LED1

LED4

MDIO

MDC

XTALI

XTALO

RDAC

REGSUP

REGOUT

TRD[3:0]+/-

CLK125_NONRGMII

3/9/2010 70LCX

B50610 Data Sheet

09/18/09

Broadcom Corporation

Page ii Document B50610-DS07-R

REVISION HISTORY

Revision Date Change Description

B50610-DS07-R

09/18/09 Updated:

• Table 1, ”Hardware Mode Selection,” on page 1

• G10, D2/H5 in Table 2, ”Hardware Signal Descriptions,” on page 11

• ”Standby Power-Down Mode” on page 21

• Note in ”CLK125 and CLK125_NONRGMII Clock Output” on page 22

• ”Ultra-Low Power-Down Mode” on page 22

• Table 14, ”48-Pin MLP Active Pin Test Function in JTAG Mode,” on page 32

• Table 16, ”48-Pin MLP RGMII Mode,” on page 33

• Table 20, ”48-Pin MLP Package RGMII Mode Selection,” on page 34

• ”LED Modes” on page 35

• Bits 15:6 in Table 47, ”1000BASE-T/100BASE-TX/10BASE-T Power/MII Control

• Bits 14:12 in Table 48, ”1000BASE-T/100BASE-TX/10BASE-T Miscellaneous

Test Register (Address 18h, Shadow Value 100),” on page 73

• ”CLK125 Output” on page 89

• ”CLK125_NONRGMII Disable” on page 95

• “Digital Pin Operating @ 3.3V or 2.5V OVDD” in Table 84, ”DC Characteristics,”

on page 119

B50610-DS06-R

06/15/09 Updated:

• ”Ethernet@Wirespeed™ Mode” on page 41

• ”Expansion Register 08H: 10BT Controls” on page 128

B50610-DS05-R 04/29/09 Updated:

• Figure 1, ”Functional Block Diagram,” on page i

• Regulator graphic in Table 3, ”Hardware Signal Descriptions,” on page 20

• ”CLK125 and CLK125_NONRGMII Clock Output” on page 37

• Table 4, ”1000BASE-T External Loopback With External Loopback Plug,” on

page 40

• Table 5, ”1000BASE-T External Loopback Without External Loopback Plug,” on

page 40

• Table 7, ”100BASE-TX External Loopback Without External Loopback Plug,” on

page 40

• Table 9, ”10BASE-T External Loopback Without External Loopback Plug,” on

page 40

• Table 13, ”Programmable LEDs,” on page 45

• ”48-Pin MLP Package Hardware Configuration” on page 46

• Table 85, ”Main Differences Between Standard and RoHS-Compliant

Packages,” on page 136

• Table 88, ”Ordering Information,” on page 140

Added:

• ”JTAG Mode” on page 46

• Table 15, ”48-Pin MLP Active Pin Test Function in JTAG Mode,” on page 47

• ”Normal Operation Mode and PHYA Mode” on page 47

• ”PHY Address” on page 47

• Table 16, ”48-Pin MLP PHY Address Based on PHYA[0] and TEST[3:2]

Settings,” on page 47

• Table 17, ”48-Pin MLP RGMII Mode,” on page 47

• ”RGMII LED Mode” on page 47

• ”LOM LED Mode” on page 48

• Table 18, ”48-Pin MLP LOM LED Link Signal Rate Reporting,” on page 48

• Table 19, ”48-Pin MLP RGMII Modes for LOM LED Operation,” on page 48

3/9/2010 70LCX

Data Sheet B50610

09/18/09

Broadcom Corporation

Document B50610-DS07-R Page iii

B50610-DS04-R 12/09/08 Updated:

• Cover page

• Figure 1, ”Functional Block Diagram,” on page i

• Table 1, ”Hardware Mode Selection,” on page 1 through Table 3, ”Hardware

Signal Descriptions,” on page 19

• Figure 4, ”Typical RGMII-to-10/100/100BASE-T Application,” on page 2

• Figure 7, ”100-Pin FBGA Pinout Diagram, Top View,” on page 29

• ”Reset” on page 34

• ”Standby Power-Down Mode” on page 35 through ”Ultra-Low Power-Down

Mode” on page 36

• Table 15, ”Using TEST[3:2] Pins to Set JTAG, Normal Operation, and PHYA

Modes,” on page 45

• Table 19, ”Register Map,” on page 52

• Table 22, ”1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register

(Addresses 02h and 03h),” on page 59

• Table 49, ”1000BASE-T/100BASE-TX/10BASE-T Register 1Ch Shadow

Values,” on page 97 and Table 50, ”1000BASE-T/100BASE-TX/10BASE-T

Spare Control 1 Register (Address 1Ch, Shadow Value 00010),” on page 98

• ”TXC/RXC Disable During Auto Power-Down Mode” on page 102

• ”External Control 1 Register” on page 108

• Table 80, ”Main Differences Between Standard and RoHS-Compliant

Packages,” on page 133

• Table 83, ”Ordering Information,” on page 137

Added:

• Figure 12, ”Internal Loopback Mode,” on page 37 through Figure 14, ”External

Loopback Mode,” on page 38

B50610-DS03-R 07/15/08 Updated:

• ”Internal Voltage Regulator” on page 8.

• Table 2, ”Hardware Signal Descriptions,” on page 11.

• Table 13, ”Programmable LEDs,” on page 43.

• ”1000BASE-T/100BASE-TX/10BASE-T PHY Identifier” on page 58.

• ”Thermal Information” on page 136.

B50610-DS02-R 06/12/08 Updated:

• RGMII HSTL voltage function in Table 1, ”Hardware Mode Selection,” on page 1

• Table 2, ”Hardware Signal Descriptions,” on page 11

• Table 2, ”Hardware Signal Descriptions,” on page 11Table 16, ”48-Pin MLP

Package RGMII Mode Selection,” on page 45

• Table 74, ”RGMII Input Timing (Normal Mode): GTXCLK and TXD[3:0],” on page

127

• Table 75, ”RGMII Input Timing (Delayed Mode): GTXCLK and TXD[3:0],” on

page 128

• Figure 16, ”RGMII Input Timing (Delayed Mode): GTXCLK and TXD[3:0],” on

page 128

• Table 76, ”RGMII Output Timing (Normal Mode): RXC and RXD[3:0],” on page

129

Revision Date Change Description

3/9/2010 70LCX

Broadcom

, the pulse logo, Connecting everything

, the Connecting everything logo, CableChecker™,

Ethernet@Wirespeed™, and BroadR-Reach™ are among the trademarks of Broadcom Corporation and/or its affiliates in

the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property

of their respective owners.

This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or

certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous

substances management, or other high risk application. BROADCOM PROVIDES THIS DATA SHEET "AS-IS", WITHOUT

WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING,

WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, AND NON-INFRINGEMENT.

Broadcom Corporation

5300 California Avenue

Irvine, CA 92617

Printed in the U.S.A.

B50610-DS02-R (cont,) 06/12/08 • Table 77, ”RGMII Output Timing (Delayed Mode): RXC and RXD[3:0],” on page

130

• Table 78, ”Absolute Maximum Ratings,” on page 131

• Table 79, ”DC Characteristics,” on page 131

• Table 80, ”Main Differences Between Standard and RoHS-Compliant

Packages,” on page 133

Added:

• Figure 7, ”BCM50610 48-Pin MLP Pinout Diagram, Top View,” on page 32

”REFCLK Input Timing” on page 125

B50610-DS01-R 04/18/08 Updated:

• Bit 15:5 in Table 24, ”1000BASE-T/100BASE-TX/10BASE-T Auto-Negotiation

Expansion Register (Address 06h),” on page 51

• Bit 8:7 in Table 41, ”10BASE-T Register (Address 18h, Shadow Value 001),” on

page 70

• Bit 15:6 in Table 42, ”1000BASE-T/100BASE-TX/10BASE-T Power/MII Control

• Bit 7:3 in Table 44, ”1000BASE-T/100BASE-TX/10BASE-T Miscellaneous

Control Register (Address 18h, Shadow Value 111),” on page 75

• Bit 1 in Table 49, ”1000BASE-T/100BASE-TX/10BASE-T Spare Control 1

• Default values in Table 55, ”1000BASE-T/100BASE-TX/10BASE-T LED Status

• Bit 2 in Table 56, ”1000BASE-T/100BASE-TX/10BASE-T LED Control Register

(Address 1Ch, Shadow Value 01001),” on page 92

B50610-DS00-R 02/28/08 Initial release.

Revision Date Change Description

3/9/2010 70LCX

Data Sheet B50610

09/18/09

Broadcom Corporation

Document B50610-DS07-R Page v

TABLE OF CONTENTS

Section 1: Functional Description......................................................................................1

Overview ....................................................................................................................................................... 1

Modes of Operation ..................................................................................................................................... 1

Reduced Gigabit Media Independent Interface......................................................................................... 2

Media Independent Interface....................................................................................................................... 2

Management Interface ................................................................................................................................. 2

Encoder......................................................................................................................................................... 2

Decoder......................................................................................................................................................... 3

Carrier Sense................................................................................................................................................ 4

Link Monitor.................................................................................................................................................. 4

Digital Adaptive Equalizer........................................................................................................................... 4

Echo Canceler .............................................................................................................................................. 4

Crosstalk Canceler....................................................................................................................................... 5

Analog-to-Digital Converter ........................................................................................................................ 5

Clock Recovery/Generator.......................................................................................................................... 5

Baseline Wander Correction....................................................................................................................... 5

Multimode TX Digital-to-Analog Converter................................................................................................ 6

Stream Cipher............................................................................................................................................... 6

Wire Map and Pair Skew Correction........................................................................................................... 7

Automatic MDI Crossover ........................................................................................................................... 7

10/100BASE-T Forced Mode Auto-MDIX.................................................................................................... 8

Auto-Negotiation.......................................................................................................................................... 8

Energy Detect............................................................................................................................................... 8

Internal Voltage Regulator .......................................................................................................................... 8

Power-Down Modes..................................................................................................................................... 9

Jumbo Packets............................................................................................................................................. 9

Section 2: Hardware Signal Descriptions........................................................................10

Section 3: Operational Description..................................................................................20

Reset ........................................................................................................................................................... 20

PHY Address .............................................................................................................................................. 20

Isolate Mode ............................................................................................................................................... 20